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Hot!Is MFINTOSC divided down from HFINTOSC?

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ReverseEMF
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2020/07/01 12:23:13 (permalink)
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Is MFINTOSC divided down from HFINTOSC?

The PIC16F15323 Datasheet is vague on this point.  Figure 9-1 implies this, but the text doesn't really, actually, say it [from sec 9.2.2.1]:
"The MFINTOSC is an internal clock source within the HFINTOSC that provides two (500 kHz, 32 kHz) constant clock outputs."
I'm uncertain because if the 500kHz and 32kHz outputs are derived from the HFINTOSC frequency, then why isn't it just called a "Postscale" of the HFINTOSC frequency?

I'm asking because I'm using the NCO and I need it to have the same "drift" as the HFINTOSC, because I plan to "calibrate" the NCO, based on a gated count from Timer1, with the T1GATE GSS set to T1GPPS to receive a signal from a different, crystal controlled MCU.  I want Timer1 to be clocked at FOSC [1MHz], but I want the NCO to run at a much lower frequency, so I can more tightly control it with the Increment [the "calibration" referred to before]. 
 
The 32kHz MFINTOSC output, if used to clock the NCO, would be an easy way to achieve this, but if it isn't derived from the HFINTOSC [i.e. if it's a separate entity, running independent of the HFINTOSC], then I would need to find a way to divide down the HFINTOSC, to get my lower frequency clock for the NCO.  I can get a 128 divide from the Reference Clock, but I would like a much lower frequency.  I could use Timer0, by feeding it through one of the CLC modules, but I'd like to avoid climbing that learning curve!

It would have been SO nice if the NCO included "Timer0 overflow output" as one of it's Clock Inputs!
post edited by ReverseEMF - 2020/07/01 12:24:17

The Electrons Flow Round and Round...
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    RISC
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    Re: Is MFINTOSC divided down from HFINTOSC? 2020/07/01 12:40:52 (permalink)
    +1 (1)
    Hi,
    According to datasheet it is clear that MFINTOSC and the 31.25kHz are derived from HFINTOSC.
    I remember that in some older devices there were 3 different oscillators, but maybe this is costly...
    But....the good news is that there is a way to do what you are looking for : running NCO from Timer0 overflow output Smile: Smile.
    Have you ever used the CLC logic gates ?
    Select 4 input AND structure for CLC1
    With the CLC1, you can select Timer0_overflow (and much more other signals) as input.
    Then select LC1OUT as NCO clock (LC1OUT is the output from above logic structure 
     
    You can do this in 5 mn using MCC plugin Smile: Smile
    Regards 

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #2
    ReverseEMF
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    Re: Is MFINTOSC divided down from HFINTOSC? 2020/07/05 09:09:39 (permalink)
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    Hi "RISC",
     
    No disrespect, but how is it clear, from the datasheet, that the 31.25kHz output on the MFINTOSC is absolutely derived from HFINTOSC?  Because there is a line drawn between them?  I don't trust lines.  Is there a place, in the text of either the datasheet, or an App Note, or a Family Reference [all I can find are documents released back in the 1990's!], that actually states that the 31.25kHz frequency is derived from the HFINTOSC?

    And, yes, I did notice the CLC angle.  I was just afraid of the Learning Curve ['cuz of the terrible amount of time it might require ;) ].  But, given your input, I feel better about giving it at try!

    Thank you! grin: grin

    The Electrons Flow Round and Round...
    #3
    upand_at_them
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    Re: Is MFINTOSC divided down from HFINTOSC? 2020/07/05 09:48:20 (permalink)
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    Yes, the drawing of the oscillator architecture is enough.  Also page 105 of the datasheet.
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    RISC
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    Re: Is MFINTOSC divided down from HFINTOSC? 2020/07/05 10:06:43 (permalink)
    +1 (1)
    Hi,
    I understand now your point. In section 9.2.2.1 it is indeed mentioned :
    "The MFINTOSC is an internal clock source within the HFINTOSC that provides two (500 kHz, 32 kHz) constant clock outputs."
    This is a document mistake (32kHz)...it should be 31.25kHz (as it is shown in figure 9.1) because it is obtained by dividing HFINTOSC by a digital value :exemple 1MHz / 32 = 31.25kHz
    => this is my personal interpretation. I encourage you to open a ticket to Microchip online technical support to have this confirmed (or not).
    To verify if MFINTOSC is derived from HFINTOSC you can put the PIC in sleep mode...
    On one side you have the separate 31kHz oscillator called LFINTOSC
    "The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source." this one is totally independant from HFINTOSC / MFINTOSC
    On the other side you can also provide an EXTERNAL 32kHz XTAL (actually 32.768kHz) also called LP oscillator specified in table 37-7 as max = 100kHz (typically 32.768kHz)
    NB: there is no way to have a 32.768kHz accurate frequency internally unless a XTAL would be added within the same physical package as it is the case in some RTC circuits (RTC IC die + 32kHz XTAL). Recent PIC16 generally have +/-2% max tolerance from 0 to 60C on any internal oscillator. This enable UART operation without usage of an external XTAL.
    Should you have still any doubt, please contact Microchip directly as this is only a public users forum Smile: Smile
    Regards
    post edited by RISC - 2020/07/05 14:39:47

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #5
    NorthGuy
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    Re: Is MFINTOSC divided down from HFINTOSC? 2020/07/05 11:47:11 (permalink)
    +3 (3)
    This is very easy to test. Just make two same frequency LED blinkers each using its own oscillator (either MFINTOSC or HFINTOSC) and see if they dissynchronize.
    post edited by NorthGuy - 2020/07/05 12:05:45
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