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Hot!dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC :

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karan123
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2020/07/01 07:49:36 (permalink)
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dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC :

Hi,
 
I have to start with dsPIC33CK256MP506 
MPLAB® Code Configurator (MCC) : Version: 3.95.0     .
But Couldn't understood FOSC as generated by MCC.
 
Please check this link and explain.
https://imgur.com/a/BHEm9as
Is this bug or what ?
 
--
Karan
 
 
#1

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    MBedder
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 08:09:06 (permalink)
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    Why not attach a picture to the post directly instead of using an external image storage site?
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    du00000001
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 08:12:28 (permalink)
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    What exactly don't you understand ?
    MCC only partly protects you from "shoot into your (own) foot".
    Might be it created a warning (other window) that Fosc etc. is beyond spec.
    But it has to allow for such excursions as otherwise the clock configuration couldn't be done at all.
     
    So lower your input frequency, increase your prescaler value or decrease your feedback divider - just make sure your PLL and output frequencies are within the allowable range.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #3
    karan123
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 08:20:51 (permalink)
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    du00000001
    What exactly don't you understand ?
    MCC only partly protects you from "shoot into your (own) foot".Might be it created a warning (other window) that Fosc etc. is beyond spec.But it has to allow for such excursions as otherwise the clock configuration couldn't be done at all. So lower your input frequency, increase your prescaler value or decrease your feedback divider - just make sure your PLL and output frequencies are within the allowable range.

    Thanks
    Means
    FOSC = 100MHz
    FCY. = 50MHz
    ?
    --
    Karan
    #4
    du00000001
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 08:28:10 (permalink)
    5 (1)
    I didn't dig into the datasheet, but FCY = 100 MHz / FOSC = 200 MHz seems appropriate considering the 100 MIPS rating of the CK family.
    (OK - the "100 MHz / 100 MIPS" data on the product page might be a bit misleading. AFAIK the dsPIC33 families still rely on FCY * 2 = FOSC, so 100 / 200 MHz should be appropriate.)
    When in doubt: first ask the datasheet! (The community better only when the datasheet/errata sheet/FRM(s) do not answer your question.)

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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    karan123
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 10:58:20 (permalink)
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    OK - the "100 MHz / 100 MIPS" data on the product page might be a bit misleading

    You mean to say dsPIC33CK can run 200MHz ? Is it?
     
    FOSC = 200MHz
    FCy    = 100MHz
     
    post edited by karan123 - 2020/07/01 11:13:55

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    du00000001
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 11:47:47 (permalink)
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    I mean if you want 100 MIPS, Fcy has to be 100 MHz.
    And as Fosc can't be less than 2 * Fcy, it has to be 200 MHz.
    BTW: What do datasheet and FRM say?

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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    Gort2015
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 12:45:10 (permalink)
    2.33 (3)
    100 MIPS = 100 MHz.
     
    FOSC is derived from the xtal, M1 and N1 - N3.
     
    Calculatons are easy done in C definitions.
     
     
     
     
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
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    RISC
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/01 13:24:33 (permalink)
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    Hi Karan,
    Your setup here is correct : https://www.microchip.com/forums/FindPost/1146206
    for dsPIC33 : Fcy = Fosc / 2
    Fosc = 200MHz => Fcy = 100 MIPS which is the max speed
    The reason why "MIPS" is used is just because most dsPIC instructions execute in 1 cycle.
    Regarding Alternate PLL this clock can be used for peripherals (look at section 9.2)
    Regards
     
     
     
     
    post edited by RISC - 2020/07/02 02:41:29

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #9
    Gort2015
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    Re: dsPIC33CK256MP506 Clock Configuration Wrong (?) with MCC : 2020/07/02 11:39:49 (permalink)
    1 (2)
    Plus some instructions can do more in 1 cycle.
    For the CH and CK @100MHz using an external 20MHz xtal.
    #define BAUDRATE    1024000
    #define M                80
    #define N1                1
    #define N2                4
    #define N3                1
    #define FPLLI      20000000                          // external xtal
    #define FVCO       (FPLLI * (M / N1))                // 1600MHz
    #define FPLLO      (FPLLI * (M / (N1 * N2 * N3)))    // 400,000,000
    #define FOSC       (FPLLO >> 1)                      // 200,000,000
    #define fcy        (FOSC  >> 1)                      // 100,000,000
    #define MIPS           fcy

     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #10
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