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Hot!PIC16LF18345 RA4 and RA5 stuck low

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JustRob
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2020/05/21 07:48:49 (permalink)
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PIC16LF18345 RA4 and RA5 stuck low

I'm using this pic in the 20 pin soic package along with MPLABX IDE v5.15, XC8 v2.05 compiler and the ICD3 in a simple two stepper motor driver application.  
 
I could swear I have configured all of the io to digital outputs (tris, lats and ansels) but when I run through some basic line toggling RA4 and RA5 are stuck low.  Ironically they are both associated to SOSCO and SOSCI.
 
Here is my main code and my system initialization code:

// PIC16LF18344 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1
#pragma config FEXTOSC = HS // FEXTOSC External Oscillator mode Selection bits (HS (crystal oscillator) above 4 MHz)
#pragma config RSTOSC = HFINT32 // Power-up default value for COSC bits (HFINTOSC with 2x PLL (32MHz))
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled; I/O or oscillator function on OSC2)
#pragma config CSWEN = OFF // Clock Switch Enable bit (The NOSC and NDIV bits cannot be changed by user software)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is disabled)

// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit (MCLR/VPP pin function is MCLR; Weak pull-up enabled)
#pragma config PWRTE = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config WDTE = OFF // Watchdog Timer Enable bits (WDT disabled; SWDTEN is ignored)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = ON // Brown-out Reset Enable bits (Brown-out Reset enabled, SBOREN bit ignored)
#pragma config BORV = LOW // Brown-out Reset Voltage selection bit (Brown-out voltage (Vbor) set to 2.45V)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a Reset)
#pragma config DEBUG = OFF // Debugger enable bit (Background debugger disabled)

// CONFIG3
#pragma config WRT = OFF // User NVM self-write protection bits (Write protection off)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.)

// CONFIG4
#pragma config CP = OFF // User NVM Program Memory Code Protection bit (User NVM code protection disabled)
#pragma config CPD = OFF // Data NVM Memory Code Protection bit (Data NVM code protection disabled)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

#include "system-resources.h"
#include "allegro-stepper-ctrl.h"
//#include "spi-16lf.h"


void main(void) {
    
    OSCCON1bits.NOSC = 0b000; // Set internal oscillator 32MHz
    OSCCON1bits.NDIV = 0b0011; // Set oscillator divider to 8 for Fcy = 4MHz
    OSCCON3bits.SOSCBE = 1; // disable secondary oscillator input
    
    system_init();
    test_x_stepper();
    test_y_stepper();
    
    
    while(1){
        
    }
}

 
My system c code and h files:

#include "system-resources.h"
#include <xc.h>


/**************************************
 *
 * Initialize the system IO
 *
*/
void system_init(){
    
    X_DIR_LATCH = RIGHT;
    X_STEP_LATCH = 0;
    X_RESETn_LATCH = 0;
    X_MS1_LATCH = 0;
    X_ENABLE_LATCH = 0;
    Y_DIR_LATCH = UP;
    Y_STEP_LATCH = 0;
    Y_RESETn_LATCH = 0;
    Y_MS1_LATCH = 0;
    Y_ENABLE_LATCH = 0;
    SPI_SCK_LATCH = 0;
    SPI_SDO_LATCH = 0;
    SPI_GYRO_CS_LATCH = 0;
    
    X_DIR_ANSEL = DIGITAL;
    X_STEP_ANSEL = DIGITAL;
    X_RESETn_ANSEL = DIGITAL;
    X_MS1_ANSEL = DIGITAL;
    X_ENABLE_ANSEL = DIGITAL;
    Y_DIR_ANSEL = DIGITAL;
    Y_STEP_ANSEL = DIGITAL;
    Y_RESETn_ANSEL = DIGITAL;
    Y_MS1_ANSEL = DIGITAL;
    Y_ENABLE_ANSEL = DIGITAL;
    SPI_SCK_ANSEL = DIGITAL;
    SPI_SDO_ANSEL = DIGITAL;
    SPI_GYRO_CS_ANSEL = DIGITAL;
    
    X_DIR_TRIS = OUTPUT; // set as output
    X_STEP_TRIS = OUTPUT; // set as output
    X_RESETn_TRIS = OUTPUT; // set as output
    X_MS1_TRIS = OUTPUT; // set as output
    X_ENABLE_TRIS = OUTPUT; // set as output
    Y_DIR_TRIS = OUTPUT; // set as output
    Y_STEP_TRIS = OUTPUT; // set as output
    Y_RESETn_TRIS = OUTPUT; // set as output
    Y_MS1_TRIS = OUTPUT; // set as output
    Y_ENABLE_TRIS = OUTPUT; // set as output
    SPI_SCK_TRIS = OUTPUT; // set as output
    SPI_SDO_TRIS = OUTPUT; // set as output
    SPI_SDI_TRIS = INPUT; // set as input
    SPI_GYRO_CS_TRIS = OUTPUT; // set as output

    X_DIR_LATCH = LEFT;
    X_STEP_LATCH = 1;
    X_RESETn_LATCH = 1;
    X_MS1_LATCH = 1;
    X_ENABLE_LATCH = 1;
    Y_DIR_LATCH = DOWN;
    Y_STEP_LATCH = 1;
    Y_RESETn_LATCH = 1;
    Y_MS1_LATCH = 1;
    Y_ENABLE_LATCH = 1;
    SPI_SCK_LATCH = 1;
    SPI_SDO_LATCH = 1;
    SPI_GYRO_CS_LATCH = 1;
    
    X_STEP_LATCH = 0;
    X_RESETn_LATCH = 1;
    X_MS1_LATCH = 1;
    X_ENABLE_LATCH = 0;
    Y_DIR_LATCH = UP;
    Y_STEP_LATCH = 0;
    Y_RESETn_LATCH = 1;
    Y_MS1_LATCH = 1;
    Y_ENABLE_LATCH = 0;
    SPI_SCK_LATCH = 0;
    SPI_SDO_LATCH = 0;

}

 

#ifndef SYSTEM_RESOURCES_H
#define SYSTEM_RESOURCES_H

#ifdef __cplusplus
extern "C" {
#endif

#define INPUT 1
#define OUTPUT 0
#define RIGHT 0
#define LEFT 1
#define UP 0
#define DOWN 1
#define FULL_STEP 0
#define HALF_STEP 1
#define ENABLE 0
#define DISABLE 1
#define ANALOG 1
#define DIGITAL 0
    
#define X_DIR_LATCH LATAbits.LATA5
#define X_STEP_LATCH LATAbits.LATA4
#define X_RESETn_LATCH LATCbits.LATC5
#define X_MS1_LATCH LATCbits.LATC4
#define X_ENABLE_LATCH LATCbits.LATC3

#define Y_DIR_LATCH LATAbits.LATA2
#define Y_STEP_LATCH LATCbits.LATC0
#define Y_RESETn_LATCH LATCbits.LATC1
#define Y_MS1_LATCH LATCbits.LATC2
#define Y_ENABLE_LATCH LATBbits.LATB7

#define SPI_SCK_LATCH LATBbits.LATB6
#define SPI_SDO_LATCH LATBbits.LATB5
#define SPI_GYRO_CS_LATCH LATCbits.LATC6

#define X_DIR_ANSEL ANSELAbits.ANSA5
#define X_STEP_ANSEL ANSELAbits.ANSA4
#define X_RESETn_ANSEL ANSELCbits.ANSC5
#define X_MS1_ANSEL ANSELCbits.ANSC4
#define X_ENABLE_ANSEL ANSELCbits.ANSC3
    
#define Y_DIR_ANSEL ANSELAbits.ANSA2
#define Y_STEP_ANSEL ANSELCbits.ANSC0
#define Y_RESETn_ANSEL ANSELCbits.ANSC1
#define Y_MS1_ANSEL ANSELCbits.ANSC2
#define Y_ENABLE_ANSEL ANSELBbits.ANSB7

#define SPI_SCK_ANSEL ANSELBbits.ANSB6
#define SPI_SDO_ANSEL ANSELBbits.ANSB5
#define SPI_GYRO_CS_ANSEL ANSELCbits.ANSC6

#define X_DIR_TRIS TRISAbits.TRISA5
#define X_STEP_TRIS TRISAbits.TRISA4
#define X_RESETn_TRIS TRISCbits.TRISC5
#define X_MS1_TRIS TRISCbits.TRISC4
#define X_ENABLE_TRIS TRISCbits.TRISC3
#define Y_DIR_TRIS TRISAbits.TRISA2
#define Y_STEP_TRIS TRISCbits.TRISC0
#define Y_RESETn_TRIS TRISCbits.TRISC1
#define Y_MS1_TRIS TRISCbits.TRISC2
#define Y_ENABLE_TRIS TRISBbits.TRISB7
#define SPI_SCK_TRIS TRISBbits.TRISB6
#define SPI_SDO_TRIS TRISBbits.TRISB5
#define SPI_SDI_TRIS TRISBbits.TRISB4
#define SPI_GYRO_CS_TRIS TRISCbits.TRISC6
    

void system_init(void);

#ifdef __cplusplus
}
#endif

#endif /* SYSTEM-RESOURCES_H */


 
I don't see what I'm missing.

Sometimes the obstacles in our path ARE our path!
 
https://abateandempower.com/
#1

5 Replies Related Threads

    du00000001
    Just Some Member
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    Re: PIC16LF18345 RA4 and RA5 stuck low 2020/05/21 08:55:15 (permalink)
    0
    Hi Rob,
     
    your projects are certainly fine to develop once the basic setup is ok. But debugging the setup can be challenging  :)
    Unfortunately I have no '1834x at hand.
     
    So let's try a different approach using the debugger:
    1. Disconnect the stepper drivers to prevent shorts. (If there's no way to disconnect these, check that they wont be damaged if the motor power supply is missing - and disconnect that one.)
    2. Load your software, set a breakpoint on the call to the 1st test routine (in main) and make the sw to run to this bp.
    3. Add the following variables to the watch window: PORTA, LATA, ANSELA, TRISA, RA4PPS, RA5PPS.
    4. RA4PPS and RA5PPS are expected to each hold 0x00.
    5. Now you can check ANSELA, TRISA, both expected to hold ..00....
    6. AND you can write the values of your choice to LATA, checking the outcome on PORTA resp. with a multimeter or a scope.
    While your system_init() hosts multiple initialization values for X_DIR_LATCH and X_STEP_LATCH, this shouldn't hurt much. Beyond that, visual checks didn't unveil an obvious problem.
    ==> Are you sure there's no external short on these pins?

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #2
    NorthGuy
    Super Member
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    Re: PIC16LF18345 RA4 and RA5 stuck low 2020/05/21 09:20:30 (permalink)
    +2 (2)
    I would set FEXTOSC to OFF in config. HS enables oscillator on OSC1 and OSC2, which are RA4 and RA5.
    #3
    RISC
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    Re: PIC16LF18345 RA4 and RA5 stuck low 2020/05/21 09:26:21 (permalink)
    +1 (1)
    Hi,
    I have tested PIC16LF18345 on Curiosity patform and toggled RA4 and RA5 using MCC ( in 30 mn ...without reading the datasheet).
    I attach the MPLAB X v5.40 / XC8 v2.20 project herewith (remove the .txt as it is a zip archive)
    Attached project toggles LED D4 and D6 (wire needed between RA2 and RA4)
    Regards
     
    post edited by RISC - 2020/05/21 09:27:41
    #4
    JustRob
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    Re: PIC16LF18345 RA4 and RA5 stuck low 2020/05/21 09:45:38 (permalink)
    0
    I tried the easiest first:
    I would set FEXTOSC to OFF in config. HS enables oscillator on OSC1 and OSC2, which are RA4 and RA5.

     
    This did it.  Now both RA4 and RA5 are toggling.
     
    And I did remove the stepper driver before with nothing connected to RA4 and RA5 with no help.
     
    Thanks yet again!

    Sometimes the obstacles in our path ARE our path!
     
    https://abateandempower.com/
    #5
    du00000001
    Just Some Member
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    Re: PIC16LF18345 RA4 and RA5 stuck low 2020/05/21 13:14:07 (permalink)
    0
    mi, mi, mi  sad
     
    I had seen the HS oscillator config and fast forgotten about that - maybe assuming that the ANSELA settings would override this selection. So I'll engrave into my grey matter that config setting might override whatever you "wish" via later settings.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #6
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