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Hot!DSPIC33CK ADC Configuration help

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Antimatter
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2020/05/17 09:51:46 (permalink)
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DSPIC33CK ADC Configuration help

Processor = DSPIC33CK64MP105

I wish to setup the shared ADC core to read the 1.2V bandgap triggered by software.

The problem I am having is to select the trigger source. The channel number being 20.

The datasheet specifies ADTRIGnL/ADTRIGnH as the register to select the channel trigger.
So is 'n' the core number? And since the shared core is last and this device has 3 cores then I specify ADTRIG2L?
Why is there a Low and a High register?

I don't get the scheme of the trigger source to channel i guess.
#1

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    du00000001
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    Re: DSPIC33CK ADC Configuration help 2020/05/17 10:55:26 (permalink)
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    In addition to the datasheet you should really read DS70005213, the "12-Bit High-Speed, Multiple SARs A/D Converter (ADC) FRM", which is intended to give generalized information while the datasheet gives the device-specific ones.
    Yours has gotten a total of 13 ADTRIG?L/H registers. (The 'x' and 'n' wildcards seem to be somewhat inconsistently within the docs - or I do not understand the scheme.) As the ADTRIG.. registers are assined to analog input channels (not ADC cores), these 13 registers could support up to 26 analog channels (19 external plus 2 internal channels available).
    Details are in the FRM. I haven't yet used a CK/CH device. Anyway, I assume that once you've got the concept of triggering channel conversions (vs. selecting an input by writing some value to an input mux register), the rest will not be too difficult.
    And no - x/n has little to nothing to do with the DAC core involved in the conversion.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #2
    JPortici
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    Re: DSPIC33CK ADC Configuration help 2020/05/17 11:04:28 (permalink)
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    Each channel require a trigger source, it's the event that will queue the acquisition (i say queue because if more than one channel connected to the shared core is triggered, they will all be converted. In sequence, of course. That's how "SCAN" is implemented in this new ADC. You can do pretty complex stuff if you dare)
     
    ADTRIG4Lbits.TRGSRC16 = 1;

    means that AN16 will queue a conversion when the selected event happens. "1" is the magic number for common software trigger (SWCTRG bit) so to queue a conversion you have to set the SWCTRG bit and wait for it to complete.
     
    How to generate the ADC interrupt signal, still in the manual (enable channel interrupt, you can get an interrupt for every channel and a more general one.. things like that.)
    #3
    Antimatter
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    Re: DSPIC33CK ADC Configuration help 2020/05/24 10:37:00 (permalink)
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    OK well lets start with a simple configuration. No interrupts. Nothing fancy. Things can be added later. 

    Only the shared core measuring one channel, channel 20, the 1.2V bandgap, since we know the value that should be read.

    Triggered by software.


        ADCON1L = 0x0000;
        ADCON1H = 0x0060;
        ADCON2L = 0x087f;
        ADCON2H = 0x03ff;
        //Channel 20
        ADCON3L = 0x0014;
        
        ADCON3H = 0x7f01;
        ADCON4L = 0x0000;
        ADCON4H = 0x0000;
        ADCON5L = 0x0001;
        ADCON5H = 0x0f00;
        ADCORE0L = 0x03ff;
        ADCORE0H = 0x037f;
        
        //Enable ADC
        //ADCON1L = 0x8000;

    // Set initialization time
    ADCON5Hbits.WARMTIME = 15;

    // Turn on ADC module
    ADCON1Lbits.ADON = 1;

    // Turn on analog power for shared core
    ADCON5Lbits.SHRPWR = 1;

    // Wait when the shared core is ready for operation
    while(ADCON5Lbits.SHRRDY == 0);

    // Turn on digital power to enable triggers to the shared core
    ADCON3Hbits.SHREN = 1;

    // Configure the common ADC clock.
    ADCON3Hbits.CLKSEL = 2; // clock from FRC oscillator
    ADCON3Hbits.CLKDIV = 0; // no clock divider (1:1)

    // Configure the cores? ADC clock.
    ADCORE0Hbits.ADCS = 0; // clock divider (1:2)
    ADCORE1Hbits.ADCS = 0; // clock divider (1:2)

    // Configure the ADC reference sources.
    ADCON3Lbits.REFSEL = 0; // AVdd as voltage reference

    // Configure the integer of fractional output format.
    ADCON1Hbits.FORM = 0; // integer format

    // Select single-ended input configuration and unsigned output format.
    ADMOD1Lbits.SIGN20 = 0;
    ADMOD1Lbits.DIFF20 = 0;


    I believe the only thing left is to define the trigger ...
     
    #4
    JPortici
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    Re: DSPIC33CK ADC Configuration help 2020/05/24 10:39:33 (permalink)
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    yes, set the desired value for TRIGSRC, give the trigger and wait for the channel ready bit to be set
    #5
    Antimatter
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    Re: DSPIC33CK ADC Configuration help 2020/05/25 09:11:21 (permalink)
    5 (1)
    Selecting the trigger source is what i don't get. The datasheet says:


    ADTRIGnL/ADTRIGnH: ADC CHANNEL TRIGGER n(x) SELECTION REGISTERS LOW AND HIGH (x = 0 TO 20; n = 0 TO 6)


     
    Looking at the DS70005213G.pdf, page 8, ADTRIG5L sets the source for channel 20. Not sure why the device specific datasheet does not show this ...

    So ADTRIG5L = 0x0001.



    #6
    JPortici
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    Re: DSPIC33CK ADC Configuration help 2020/05/25 10:24:19 (permalink)
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    But it does!
    DS70005363D Register 12-26
    And i'd rather write ADTRIG5Lbits.TRGSRC20 = 1
     
    (Or, if you wanted to skim the device specific include file and search for TRGSRC20..)
    post edited by JPortici - 2020/05/25 10:25:27
    #7
    Antimatter
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    Re: DSPIC33CK ADC Configuration help 2020/05/25 17:51:29 (permalink)
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    OK so that wasn't so bad. Here's a minimal configuration that I used to get going. Maybe it will help someone out.


    //my defaults
    //I haven't cleaned them up yet

    //Clock source is Fosc

    ADCON1L = 0x0000;
    ADCON1H = 0x0060;
    ADCON2L = 0x007f;
    ADCON2H = 0x03ff;
    ADCON3L = 0x0000;
    ADCON3H = 0x7f01;
    ADCON4L = 0x0000;
    ADCON4H = 0x0000;
    ADCON5L = 0x0001;
    ADCON5H = 0x0f00;
    ADCORE0L = 0x03ff;
    ADCORE0H = 0x037f;

    //enable cores
    ADCON3Hbits.SHREN = 1;

    // Set initialization time
    ADCON5Hbits.WARMTIME = 4;

     

    //turn on ADC
    ADCON1Lbits.ADON = 1;

     

    // Turn on analog power for shared core
    ADCON5Lbits.SHRPWR = 1;

     

    // Wait when the shared core is ready for operation
    while(ADCON5Lbits.SHRRDY == 0);

     

    // trigger for channel 20: common software
    ADTRIG5L = 0x0001;


    //set Channel 20
    ADCON3Lbits.CNVCHSEL = 20;


    ADCON3Lbits.SHRSAMP = 1;

     

    //Read ADC
    ADCON3Lbits.CNVRTCH = 1;


    //ADCBUF20 should now contain a value equal to 1.2V
    //I got 1502 in my application

    //depends on the exact value of Vdd



    Thanks!
    post edited by Antimatter - 2020/05/25 17:53:39
    #8
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