WINC1500 sometimes fails to read CLOCKS_EN_REG
Got some problems with running latest MLA driver for WINC1500 with a PIC18F47K42 on a custom board (build in a very similar way as the Microchip devel tools). The WINC is running as an AP and main state machine is a UDP server.
After stating up the AP, opening&binding the socket, successfully receiving a datagram, at the first sendto , the ChipWake() routine reads CLOCKS_EN_REG == 0 and after several retries the winc host driver reports Error for the sendto but the winc state is damaged enough so a restart is needed.
Same ChipWake(), used by hif_send() , behaves properly for the previous SPI operations and the reported CLOCKS_EN_REG is 7.
The workaround is to add a delay ( first DelayMs(2), the second is from the original MLA). After that everything works.
volatile uint32_t reg = 0, clk_status_reg = 0, trials = 0;
//printf("[redlog] Inside ChipWake\r\n");
reg = nm_read_reg(HOST_CORT_COMM);
//printf("[redlog] Inside ChipWake: HOST_CORT_COMM = %x\r\n", reg);
if(!(reg & NBIT0))
// use bit 0 to indicate host wakeup
nm_write_reg(HOST_CORT_COMM, reg | NBIT0);
reg = nm_read_reg(WAKE_CLK_REG);
//printf("[redlog] Inside ChipWake: WAKE_CLK_REG = %x\r\n", reg);
// Set bit 1
if(!(reg & NBIT1))
nm_write_reg(WAKE_CLK_REG, reg | NBIT1);
clk_status_reg = nm_read_reg(CLOCKS_EN_REG);
printf("[redlog] Inside ChipWake: CLOCKS_EN_REG = %x\r\n", clk_status_reg);
if(clk_status_reg & NBIT2)
if(trials > WAKUP_TRAILS_TIMEOUT)
dprintf("Failed to wakup the chip\n");
// workaround sometimes spi fail to read clock regs after reading/writing clockless registers
I am of course worried about the last comment from the MLA designer : "sometimes spi fail to read ...".
My questions are:
1) did anybody had such timing issues ?
2) I need to understand why the delay fixed the problem, but I was not able to find detailed timing spec sheets for winc . I do not know what are the design rules for reading clockless registers and how far I am from breaking them.