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Hot!errors in the simulator model for PIC18FxxQ43

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Mark Yampolsky
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2020/04/10 23:14:20 (permalink)
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errors in the simulator model for PIC18FxxQ43

Hi!
I started the project on PIC18F27Q43 and found that the simulator mistakenly interprets the RAM space model in the direct mode "access". As I understand it, the error is due to the fact that the SFR-space has moved to the upper RAM addresses. The simulator continues to consider the ACCESS space located starting at physical address 0, as it was in the K22 family. Therefore, register modification in ACCESS mode is not possible.
The second mistake I noticed is incorrect support for VIC. I was unable to get the simulator to go over the vector defined by the IVTBASE register. Unlocking 0x55-0xAA does not help. The PC takes somewhere far and wrong, and the IVTAD register always gets the value 0xC000.
Used MPLAB X ver5.35 and MPASMWIN v5.87
 
 
 
post edited by Mark Yampolsky - 2020/04/10 23:24:12
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    Mark Yampolsky
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    Re: errors in the simulator model for PIC18FxxQ43 2020/04/16 23:17:08 (permalink)
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    A slight correction for ACCESS mode. I found out that only access to RAM is simulated and only in the mode of extended instructions included. And it does not depend on whether the extended instructions mode is enabled or not. That is, when FSR2=0x0500 access to GPR 0x500...0x55F appears, but no access to SFR  0x460...0x4FF.
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    JackZhao
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    Re: errors in the simulator model for PIC18FxxQ43 2020/04/21 10:21:05 (permalink)
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    Simulator team already noticed the new variant access bank in PIC18FxxQ43 devices and implemented it couple months. This change wasn't included in v5.35, but it should be in the next release v5.40. By the way, when you report a Simulator issue, we will see it much quicker if you post it in the "MPLAB Simulator". We also want to address the VIC issue you reported. Could you post a simple program which will reproduce the issue?
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    Mark Yampolsky
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    Re: errors in the simulator model for PIC18FxxQ43 2020/04/21 22:30:41 (permalink)
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    I apologize for the confusion with the forum thread. I promise to continue to improve ... )))
    IVC simulation error example.
    The link has three screenshots of the execution steps with comments and the source code in MPASM.
    I give a link to my OneDrive: https://1drv.ms/u/s!AvtgEBWH91DLg0FSJxXom_yDmjCl?e=i6yGCP
     
     
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    JackZhao
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    Re: errors in the simulator model for PIC18FxxQ43 2020/04/22 17:20:40 (permalink)
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    OK, I believe the value in VITAD probably is wrong, but I think the ISR location might also not be the place you expected. The program has 0x400 for VITBASE, so the interrupt vector address for TMR2 should be 0x436. This also should be the value in VITAD. Now please notice in 9.2.2 INTERRUPT VECTOR TABLE CONTENTS section under MVECEN = 1 (The test program does set MVECEN to 1), "When MVECEN = 1, the value in the vector table of each interrupt, points to the address location of the first instruction of the interrupt service routine. ISR Location = Interrupt Vector Table entry << 2". In the test program, the value in address 0x436 is 0xF000, so the ISR for TMR2 starts at 0x1C000. Simulator put 0x1C000 into VITAD, and the data file does not have VITAD right (only 16-bit like the VITAD in K22 family, not 20-bit), so you see the 0xC000 in VITBASE. The VIC implementation is based on K22 (the Q43 datasheet for this part agree with the K22 datasheet), and I believe that we did test that compare our simulation with the K22 hardware. I would like to test the Q43 with real hardware to prove it. Unfortunately the whole team is working from home now. If you have a hardware and prove that my assumption is wrong, we are more than happy to fix it. Also thanks for reporting the issue.
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    Mark Yampolsky
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    Re: errors in the simulator model for PIC18FxxQ43 2020/04/22 22:12:06 (permalink)
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    Thanks a lot, Jack! With your help, I found my mistake. The issue with the IVC is being removed. However, another question arose, but I will post it in another topic.
    My regards.
    post edited by Mark Yampolsky - 2020/04/22 22:13:24
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