Re: errors in the simulator model for PIC18FxxQ43
OK, I believe the value in VITAD probably is wrong, but I think the ISR location might also not be the place you expected. The program has 0x400 for VITBASE, so the interrupt vector address for TMR2 should be 0x436. This also should be the value in VITAD. Now please notice in 9.2.2 INTERRUPT VECTOR TABLE CONTENTS section under MVECEN = 1 (The test program does set MVECEN to 1), "When MVECEN = 1, the value in the vector table of each interrupt, points to the address location of the first instruction of the interrupt service routine. ISR Location = Interrupt Vector Table entry << 2". In the test program, the value in address 0x436 is 0xF000, so the ISR for TMR2 starts at 0x1C000. Simulator put 0x1C000 into VITAD, and the data file does not have VITAD right (only 16-bit like the VITAD in K22 family, not 20-bit), so you see the 0xC000 in VITBASE. The VIC implementation is based on K22 (the Q43 datasheet for this part agree with the K22 datasheet), and I believe that we did test that compare our simulation with the K22 hardware. I would like to test the Q43 with real hardware to prove it. Unfortunately the whole team is working from home now. If you have a hardware and prove that my assumption is wrong, we are more than happy to fix it. Also thanks for reporting the issue.