I am having difficulty using the SY8701A CDR…
I am feeding in serial data at 167MHz so FreqSel is set to 110b (ratio 6)
I am supplying a RefClk of 16.7MHz so DivSel is 10b (ratio 10)
I do not seem to get any output but LFIN is high
If I set ClkSel low, I get a very strange output from RClk of 167MHz divided by 60 and extremely slow RData
According to the data sheet, ClkSel only affects TClk not Rclk
I did not take TClk into my FPGA so I cannot tell what comes out
Here are the Xilinx Chipscope waveforms, the Chipscope clock is 167MHz.
What on earth is going on?