The sequence of clock switching between the primary clock (CLK1) and the secondary clock (CLK2) is explained in Microsemi_SmartFusion2_IGLOO2_Clocking_Resources_User_Guide_UG0449 section 22.214.171.124.https://www.microsemi.com/document-portal/doc_download/132012-ug0449-smartfusion2-and-igloo2-clocking-resources-user-guide
The NGMUX provides a special switching sequence between two asynchronous clocks without generating any unwanted narrow clock pulses on the output clock. There are four NGMUX blocks in a fabric CCC and each NGMUX produces one fabric CCC output clock (GLx/Yx).
Internally, there are two multiplexers to select primary and secondary clocks from the available clock sources. The primary clock source and secondary clock source to NGMUX can come from any of the following clock sources:
• On-chip oscillators
• FPGA fabric
• Dedicated global I/O pads
• 8 PLL outputs
• GPDs outputs
The primary clock and secondary clock source must generate free-running clocks without any glitches for glitch free clock switching.
If not, the NGMUX may still produce unwanted glitches on the output clock. The requirements for a successful clock switching are:
1. The primary and second clocks must be toggled during the switching operation.
2. NGMUX_SEL signal must not be switched when the previous switch is still under-going and not yet completed.
Hope this wll help you detect failure conditions of a fabric CCC .