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Hot!DMA - is it generally considered stable?

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henkebenke
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2020/03/10 13:17:53 (permalink)
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DMA - is it generally considered stable?

Hi, again.
 
Is the DMA of dsPIC's really stable? Over the years, I have had problem with glitches, etc, using the DMA in conjunction with the SPI. I haven't used DMA on other peripherals. Yesterday, I made yet another attempt, but in a way that really should be 100% safe. And it seemed fine - for a while. Then subtle spikes was seen on the scope every ten seconds or so. Very tiny, but absolutely spikes. The same algorithms, but no DMA, and the spikes were gone.
I'm using four DMA channels, and the timing is uncritical - it doesn't matter if the data arrives a us sooner or later. But all four DMA was triggered by the same T5 interrupt, and possibly that was too much for the coordination circuitry.
 
The spikes were seen on both a FIR output and an IIR output, but not on the unfiltered signal. Since the IIR/FIR algorithms works fine normally, one can suspect that the CPU perhaps becomes "confused" when there are circulating a lot of pending requests, etc...
Especially, I suspect that DMA collisions causes trouble, even if the manual states otherwise.
 
So, I'm abandoning DMA for good now, I think, but it might be interesting to hear what others has experienced. 
 
I forgot - it's a dspic33ep512gp806 device. And I used the DPS-ram.
 
#1

19 Replies Related Threads

    Gort2015
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    Re: DMA - is it generally considered stable? 2020/03/10 13:50:08 (permalink)
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    DMA - no problems at all.
    With the CK/CH chips CPU has priority over DMA.
     
    Let's elaborate on that - CPUs do not get confused.
     
     
    The EP errta, if it's that bad change to a different chip.
    post edited by Gort2015 - 2020/03/10 13:52:05

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #2
    Gort2015
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    Re: DMA - is it generally considered stable? 2020/03/10 13:53:53 (permalink)
    4 (1)
    What other faults will you discover next?

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #3
    NorthGuy
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    Re: DMA - is it generally considered stable? 2020/03/10 14:51:29 (permalink)
    5 (1)
    I've never had any problems with PIC24 DMA.
    #4
    JPortici
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    Re: DMA - is it generally considered stable? 2020/03/10 15:38:06 (permalink)
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    And yet again no code to be examined
    #5
    henkebenke
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    Re: DMA - is it generally considered stable? 2020/03/11 09:00:33 (permalink)
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    Sorry, I haven't give any code example cause I thought you might be bored. :)
     
    But the whole thing is complex, so i'd better describe it in words.
    I couldn't resist making some more tests today. I have a SPI slave stream - the clk is around 6Mhz. Continuous operation, TX. Earlier tests have been unsuccessful when using DMA. It seems that DMA requests happens at the exact point where the SPI SR has shifted out all bits, and therefore the DMA module has only a couple of CPU cycles of time to load the SR with a new value( at 6Mhz), and that's OK if the DMA has a high priority, but a DMA channel has a lower priority there will be data losses.
    I planned a workaround, I'm using T4, synced at the clock stream ( PR4 set to 15 ) with some bit offset. This timer triggers the DMA TX in the middle of the word that is currently shifted out. No timing errors will occur.
    But it doesn't work. This is an audio stream, and with an interval of a couple of seconds, the sine wave starts to "tremor".  I discovered that these intervals coincided with the DCI req from the input stream.  The input stream is not synced with the output, so if there is a 10 ppm offset, the DCI req sometimes happens when the DMA transfer occurs.
    Well, the point is that it's obvious that the "tremors" is a result of that the DMA operation in some way becomes corrupted by the input stream, since they happen at the same interval as the input/output stream skew. Or vice versa, but this is hard to examine.
    The exact same code but without DMA has no such tremors.
     
    It's really not a big deal for me. But it has become personal. I wan't to defeat the DMA.
     
     
     
    #6
    henkebenke
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    Re: DMA - is it generally considered stable? 2020/03/11 11:34:04 (permalink)
    5 (1)
    I must give you the next chapter of the story.
    I disabled nested interrupts, and the tremors were gone. This makes you think som register wasn't saved properly, but no, everything is OK. So I experimented back and forth and found that the tremors arose when the DMA isr was active. But since I'm cynical, I said to my self;  "Well if I'll go back to nested interrupts again, the whole thing with tremors, etc, will probably be gone".
    And it was.
    This supports my belief that microcontrollers are living things. Yesterday I was a bit harsh towards it, and it went sour. 
      
    #7
    Gort2015
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    Re: DMA - is it generally considered stable? 2020/03/11 14:55:27 (permalink)
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    Probably best to switch to the newer CH chips.
     
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #8
    henkebenke
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    Re: DMA - is it generally considered stable? 2020/03/15 17:28:18 (permalink)
    5 (1)
    Well, I think I'm obliged to tell you how this story ended.
    The DMA actually worked properly, but it seems that it triggered some other side effects. The culprit was the DCI interface that receives the I2S stream. It has a flaw, that is documented bu Mchip, but I still think is a flaw - it can't keep track of right and left channel. So the CPU must poll the port where the LR-clock is connected. But when there is a lot of activity, it's not sure that the DCI -isr responds quick enough to poll the port. The obvious solution is to give the DCI highest priority, but the strange thing is that it still had problems with latency. Enormous latency - a couple of us. I tried to analyze it, but both I and the circuit was in the worst of moods. The more I subjected it to testing, the more contradicting the results were. I never managed to find out what was going on, so I gave up, and found a workaround instead. 
    Since the Left/Right substituted samples comes with a ratio of 1/1000 appr, I used a simple lowpass filter that found out the proper polarity. I declared a counter, and when the LR signal was high, it increments, and vice versa when the LR was low, so it was some sort of majority decision. 
    But I still think the DMA in some way is involved in this matter. When I used direct SPI transfer, there were no problems, but with DMA, suddenly those strange latencies emerged.
    But the contraption works now. It manages to make 32 bit, sixth order IIR filtering in stereo at 192k SR. The CPU is loaded to around 94%. I don't really need sixth order, but I got caught by the challenge. 
     
    #9
    Gort2015
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    Re: DMA - is it generally considered stable? 2020/03/15 19:43:26 (permalink)
    5 (1)
    DMA always seems like magic, doing stuff while the cpu continues.
    There is only 1 bus and that is shared with the cpu.
     
    Code has to be written around that.
     
    On the newer chips, cpu gets priority.
     
    I've ran dma tests with several dma channels moving data from memory to memory.
     
    With 2 dma channels moving the same data (half each) I found the gain to be in the nano-second range.  It's down to the cpu and dma arbitrator.
     
    Logic 2 from Saleae is good for this except for the "app" look.
    Zoom in and measure time and freq.
     
    Looking at the output from dma and other logic it all runs like clockwork.
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #10
    marcov
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    Re: DMA - is it generally considered stable? 2020/03/16 06:47:16 (permalink)
    3 (1)
    (nope, some dspics have dual ported ram)
    #11
    Gort2015
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    Re: DMA - is it generally considered stable? 2020/03/16 08:31:18 (permalink)
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    Instead of "nope", Which models?
     
    I would be interested in an independent dma bus.

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #12
    crosland
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    Re: DMA - is it generally considered stable? 2020/03/16 08:47:01 (permalink)
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    Gort2015
    On the newer chips, cpu gets priority.

    Unless it's configurable this is not always the best design choice. If you are anywhere near pushing the envelope then you want the DMA to have guaranteed access and not be held back by the CPU. CPU caches help but not entirely.
     
    #13
    marcov
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    Re: DMA - is it generally considered stable? 2020/03/16 09:15:53 (permalink)
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    Gort2015
    Instead of "nope", Which models?

     
    Afaik most dspicf mc+gp, and dspice mu/gm/gp models.
     
    But you said you used GP with dps ram, but at the same time you are discussing bus arbitration of ch/cm and pic32mk.
     
    Note that the dspic33e and f have some issues with not being able to send bytes/words back-to-back. (at 8MHz  there is about 2 bit time periods room between each dmaed byte/word element). I only did detail testing as master, but maybe the analog timing problem on the receive side disturbs your slave spi 
     
    The dspic C series doesn't seem to suffer from this.
     
    post edited by marcov - 2020/03/17 05:39:09
    #14
    jtemples
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    Re: DMA - is it generally considered stable? 2020/03/16 09:26:49 (permalink)
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    High-end PIC24E also has dual ported RAM.
    #15
    T Yorky
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    Re: DMA - is it generally considered stable? 2020/03/16 11:24:14 (permalink)
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    Just for info, the ops dspic33ep512gp806 which is in the same family as the 256MU806 that I have used, has Dual port DMA memory and peripherals with a dedicated DMA bus for data and addresses. In addition the DMA can access normal RAM using an CPU arbiter (but not non-dma peripherals). I do remember some issues to avoid. Using the flash programming with DMA. Ensuring that the DMA does not index from DMA memory to non-DMA memory and vice versa. Impossible to identify the problem without code.
    T Yorky.
    #16
    nigelwright7557
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    Re: DMA - is it generally considered stable? 2020/03/16 12:56:09 (permalink)
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    The only problem I have had with PIC32MZ DMA is it doesn't update the cache so the buffer must be made coherent.
     
     
    #17
    JPortici
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    Re: DMA - is it generally considered stable? 2020/03/25 05:59:30 (permalink)
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    T YorkyImpossible to identify the problem without code.

    This.
    But don't hold your breath
    #18
    RISC
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    Re: DMA - is it generally considered stable? 2020/03/25 11:01:00 (permalink)
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    Hi henkebenke
    You said "The CPU is loaded to around 94%". That is extremely high and you should really aim to move to a more powerful dsPIC like the recent dsPIC33CH or CK which run @ 90MHz/100MHz
    I have used DMA for years without issues but never with such high CPU load.
    Their main beauty to my eyes is that because it is a simple transfer, NO CODE execution takes place and therefore nothing bad as it usually happens in interrupts.
    The "only" caveat is that when CPU load gets really high, it needs to be checked extremely carefully who has the priority between DMA, CPU,... so this is the time to move up to a faster device... 
    Regards
    #19
    stevenpostma
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    Re: DMA - is it generally considered stable? 2020/03/25 14:08:15 (permalink)
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    maybe a stupid suggestion, but do you use a CPU sleep where possible?
    a CPU doing a constant idle loop also causes a high CPU load...
    #20
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