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Helpful ReplyBizarre instruction set code for MOVLB - largest 16F18 families

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RobinAbbott
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2020/03/10 01:22:00 (permalink)
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Bizarre instruction set code for MOVLB - largest 16F18 families

So writing some code for the 16F18455 when I noticed that the instruction set is somewhat confusing for this device which has a 64 page memory (previous devices had 32 page)
 
MOVLB k - has the code 00 0000 00kk kkkk (it's a 6 bit code for k even though it's described as 5 or 6 bit at different points). In previous devices it was 00 0000 001k kkkk (for a 5 bit code for k)


which means :

MOVLB 0 - has the same code as NOP
MOVLB 0xb  - has the same code as BRW
 
There are others. Any idea what's going on ?
#1
crosland
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 02:43:13 (permalink)
+1 (3)
Where are you getting your information?
 
The data sheet has an obvious error in the instructions set summary giving only 11 bits for MOVLB.
 
It also gives BRW as 0x000B which in no way resembles MOVLB 0.
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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 03:57:34 (permalink)
+1 (1)
Yep, obvious error in the datasheet.  I would be opening a ticket to get it corrected.
 
At a pure guess, based on presumed compatibility with the existing Enhanced mid-range core devices 14 bit coding...
00 0000 001k kkkk     MOVLB k             BSR ← k, move literal to bank select register (0-31)
00 0000 010k kkkk     MOVLB k             BSR ← k, move literal to bank select register (32-63)

 
If you need a quick answer, it would also be very easy to use the assembler and find out what instructions it generates for banks 0-31 and 32-63.
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ric
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 04:14:13 (permalink)
+2 (2)
I looked through a lot of incorrect datasheets, which mostly showed
00 000 0k kkkk (only 11 bits)
until I looked in the PIC16F18857 datasheet, which shows
00 0001 01kk kkkk (14 bits)
which I assume is correct.
I'm amazed the incorrect data has been cut and pasted so often.
 
post edited by ric - 2020/03/10 04:16:33

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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 04:21:37 (permalink)
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But, at least according to Wikipedia 00 0001 is the CLR instruction...
00 0001    dfff ffff    CLR f,d         Z     dest ← 0, usually written CLRW or CLRF f

I do grant you that Wilipedia is no guardian of the Microchip instruction set encodings, but it does seem a trifle more accurate than the PIC datasheets these days...
 
Edit: Ah yes, I see.  When d=0 fffffff is unused.  So that opens up some more encodings.  I think ric is right.
post edited by pcbbc - 2020/03/10 04:27:24
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ric
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 04:29:42 (permalink)
+1 (1)
The 18857 sheet says CLRF is
00 0001 1fff ffff
and CLRW is
00 0001 0000 00xx
So neither clashes with
00 0001 01kk kkkk
 

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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 04:46:19 (permalink)
+1 (1)
Yep, makes sense now...
 
For Mid-range core devices (14 bit):
00 0001    dfff ffff     CLR f,d         Z     dest ← 0, usually written CLRW or CLRF f

So here there are 128 different encodings for CLRW as when d=0 fffffff are redundant.
 
But then to encode the new MOVLB on Enhanced mid-range core devices (14 bit) the redundant encodings of CLRW were re-purposed...
00 0001    1fff ffff     CLR f,F         Z     dest ← 0, usually written CLRF f
00 0001    0000 00xx     CLRW             Z     dest ← 0, usually written CLRW
00 0001    01kk kkkk    MOVLB k                BSR ← k, move literal to bank select register

The number of k bits will vary from device to device, depending on number of banks.  And so probably also the choice of which "spare" bit in the encoding should be set ON to differentiate from a CLRW.
 
Hence:
00 0000 001k kkkk     MOVLB k             BSR ← k, move literal to bank select register (0-31)

Is a legal encoding on a 32 bank device since bit 5 is not used for the bank.
 
I wonder if this has always been the case, or the 1 bit that is set on has moved to the higher order bits in newer devices as the number of banks increase?
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1and0
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 06:32:59 (permalink) ☄ Helpfulby RobinAbbott 2020/03/10 07:52:04
+3 (3)
ric
until I looked in the PIC16F18857 datasheet, which shows
00 0001 01kk kkkk (14 bits)
which I assume is correct.

I just confirmed that is correct with the latest MPASM v5.87 using this:
        org     0x0000
    variable k = 0
    while (k < .64)
        movlb   k
k++
    endw
        end

 

I'm amazed the incorrect data has been cut and pasted so often.

Somehow I'm not surprised. :(
 
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RobinAbbott
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 08:03:58 (permalink)
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That's very helpful, solved it ! I spent some considerable time looking at data sheets for devices with 6 bit BSR's and all the examples were wrong - I'd not discovered the 18857 datasheet which is correct !
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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 10:10:45 (permalink)
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1and0I just confirmed that is correct with the latest MPASM v5.87

That with the PIC16F18857?
 
What about devices with less banks?  Let's say 32 banks?  Does that produce...
00 0001    010k kkkk    MOVLB k                BSR ← k, move literal to bank select register

..or...
00 0001    001k kkkk    MOVLB k                BSR ← k, move literal to bank select register

 
Once might expect the former, unless of course the MC designers didn't anticipate ever having a 64 bank device.
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1and0
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 10:41:33 (permalink)
+1 (1)
pcbbc
1and0I just confirmed that is correct with the latest MPASM v5.87

That with the PIC16F18857?

Checked it with both 16F18455 and 16F18857.
 

What about devices with less banks?  Let's say 32 banks?  Does that produce...
00 0001    010k kkkk    MOVLB k                BSR ← k, move literal to bank select register

..or...
00 0001    001k kkkk    MOVLB k                BSR ← k, move literal to bank select register

Once might expect the former, unless of course the MC designers didn't anticipate ever having a 64 bank device.

Checked this with 16F1847 which has 32 banks, and it is the latter neither. It is
00 0000 001k kkkk

as specified in the datasheet.
 
Edit: Bit 8 of the opcode is not a '1' so it is neither of your opcodes.
 
post edited by 1and0 - 2020/03/10 11:15:20
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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 11:37:10 (permalink)
+2 (2)
So there are actually 2 encodings for MOVLB on Enhanced Mid-range devices.  One for devices with 32 banks:
00 0000 001k kkkk
The 9-bit prefix 00 0000 001 was unassigned in the Baseline Mid-range devices.
 
And one for Enhanced Mid-range devices with 64 banks:
00 0001 01kk kkkk
Which uses some of the unused encodings previously occupied by CLRW, which must now be encoded as:
00 0001 0000 00xx
 
It's all a bit of a mess, isn't it?!
I suppose nowhere near as bad as x86/x64....
 
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1and0
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/10 11:47:37 (permalink)
+1 (1)
pcbbc
It's all a bit of a mess, isn't it?!

Lack of planning during design stages?  Hindsight is 20/20. ;)
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crosland
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/11 09:28:19 (permalink)
+2 (2)
No one will ever need more than 32 banks of RAM :)
 
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pcbbc
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Re: Bizarre instruction set code for MOVLB - largest 16F18 families 2020/03/11 10:29:59 (permalink)
+1 (1)
croslandNo one will ever need more than 32 banks of RAM :)

Hey Hey, 16k
What does that get you these days?
You need more than that for a letter
 
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