Attached is an oscilloscope capture of the STOP bit circuit in action. Channel 1, top yellow trace, is SCL at 5 volts per division. The transfer of the last two bytes is shown, and after, the clock signal goes high so the STOP can be signaled.
Channel 2, the middle magenta trace, is SDA at 2 volts per division. You can see the bits for the last two bytes and the rising edge when SCL is high, which is the STOP.
Channel 3, the bottom blue trace at 2 volts per division, is the output of the STOP detector, the design of which is shown in an earlier message in this thread. Note that the SDA signal is rather clean, this is important since that line is used as a rising edge clock on the STOP detection circuit. As a safeguard, you may want to check I2CxSTATbits.P as a double check, this bit will be ON if the STOP is valid.
Below is a listing of the interrupts that occur when receiving a message with the STOP circuit functioning.
mode=0 indicates slave IDLE mode, mode=3 indicates slave message receiving mode.
1 mode=0, I2C2STAT=0x0208 RVC=0x00 the address byte interrupt
2 mode=3, I2C2STAT=0x0228 RVC=0x02 data bytes arrive
3 mode=3, I2C2STAT=0x0228 RVC=0x00
4 mode=3, I2C2STAT=0x0228 RVC=0x08
5 mode=3, I2C2STAT=0x0228 RVC=0x06
6 mode=3, I2C2STAT=0x0228 RVC=0x3A
7 mode=3, I2C2STAT=0x0228 RVC=0x1F
8 mode=3, I2C2STAT=0x0228 RVC=0x14
9 mode=3, I2C2STAT=0x0228 RVC=0x14
10 mode=3, I2C2STAT=0x0228 RVC=0x03
11 mode=3, I2C2STAT=0x0228 RVC=0x02
12 mode=3, I2C2STAT=0x0228 RVC=0x05
13 mode=3, I2C2STAT=0x0228 RVC=0x10
14 mode=3, I2C2STAT=0x0228 RVC=0x6D
15 mode=3, I2C2STAT=0x0228 RVC=0x18
16 mode=3, I2C2STAT=0x0228 RVC=0x01 last data byte arrives
17 mode=3, I2C2STAT=0x0030 the STOP interrupt occurs here
this gap in time can be considerable, so arrival of the next address byte is not a reasonable
signal that the prior message is complete
18 mode=0, I2C2STAT=0x0208 RVC=0x00 the address bye of the next message
19 mode=3, I2C2STAT=0x0228 RVC=0x02
20 mode=3, I2C2STAT=0x0228 RVC=0x00
21 mode=3, I2C2STAT=0x0228 RVC=0x08
Note: the data bytes above do not match the 'scope traces, since the data capture and the oscilloscope could not be easily synchronized. Also note that the 'scope is not showing the decoded data, since it was set to display only the end of a message, not including the START bit. Lastly, note that without the external STOP circuit, the listing above would be missing interrupt #17.
post edited by robert.galaxy - 2020/03/02 07:05:08