• AVR Freaks

Hot!I2C Stop bit

Author
robert.galaxy
CTO
  • Total Posts : 24
  • Reward points : 0
  • Joined: 2019/12/28 20:45:42
  • Location: East Coast
  • Status: offline
2020/02/29 15:14:52 (permalink)
0

I2C Stop bit

I have noticed many posts regarding the lack of access to the I2C STOP signal status on PIC32 chips (and other chips).  Mostly the replies are about how to change your situation so you do not need access to the STOP signal.  Apparently some people do not think this signal is needed.  "Please explain why you need this" and such.  (I do notice that at least some PIC32MZ chips seem to have this signal available, BTW.)
 
Anyway, in my case I really do need to know when the STOP signal occurs on the I2C bus.  I have a multi-master system where each master needs to act as a master at times, and a slave at other times.  In addition, the messages utilize the restart feature so that write-read operations can complete without having to release the bus between and the messages are variable length, and while the length is given as part of each message, it occurs near the end of the message, and I am not able to change the message structures. 
 
I am using the PIC32MX795F512L which does not have this signal available.  Anyway, I have come up with a very simple circuit to provide this information.  Just take the output of the circuit and connect it to a CN or INT pin.  
 
See attached, perhaps this will help someone...

Attached Image(s)

#1

6 Replies Related Threads

    Gort2015
    Klaatu Barada Nikto
    • Total Posts : 3835
    • Reward points : 0
    • Joined: 2015/04/30 10:49:57
    • Location: 0
    • Status: offline
    Re: I2C Stop bit 2020/02/29 16:24:21 (permalink)
    0
    Did you test if an interrtupt was caused by stop ?
    by checking STAT.P ?
     
    The start bit will be set through out the message meaning that we can get repeated interrupts.
    I do not use this bit, it is fine on receipt of message to do something once only.
     
    When stop event occurs, the stop bit is set, start bit cleared. Auto.
     
    It has these two missing interrupts for such a powerful chip.
    SCIE      ;start cond. int.  (Maybe a slow chip needs time to wake from sleep, rare)
    PCIE      ;stop cond. int.   (Double check STAT.P)
     
    Spurious stop interrupts can appear on the bus(usually on chip power up) but they are ignored.
    If reading, master sends a NAK when done.  Slave sleeps or waits for stop event.
     
    When writing, we need that stop bit to end the message.
     
    I'm sure with more time you would get it working in software.
     
    post edited by Gort2015 - 2020/02/29 16:28:00

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #2
    robert.galaxy
    CTO
    • Total Posts : 24
    • Reward points : 0
    • Joined: 2019/12/28 20:45:42
    • Location: East Coast
    • Status: offline
    Re: I2C Stop bit 2020/02/29 18:03:46 (permalink)
    0
    @Gort2015   Thank you for your comments. I did check, I2CxSTATbits.P does not cause an interrupt, unfortunately.    I think one would need I2CxCONbits.PCIE to get the interrupt.  And that bit does not exists on the chip I am using.
     
    The START and the REPEATED STARTS come "with" an interrupt when the address arrives. They can be identified just by looking at a couple of status bits, namely I2CxSTATbits.D_A and I2CxSTATbits.S  but the STOP comes with no interrupt at all.  Using a Scope, I see that the I2CxSTATbits.P can arrive a long time after the last interrupt, which occurs with the last data byte..  The next interrupt will not come until an ADDRESS char as part of another message.  That could be a a LONG time, or perhaps even never, if there are no more messages to deliver.  It is not reasonable to have the interrupt handler use a "spin loop" waiting for the I2CxSTATbits.P bit to be set.
     
    My plan is to have a CN interrupt routine call the I2C interrupt routine, as if an I2C interrupt was indeed caused by the P bit.  When this call happens, the P bit will already be set.  Hopefully it will work...I should know later this weekend.....:)
    post edited by robert.galaxy - 2020/02/29 18:07:16
    #3
    robert.galaxy
    CTO
    • Total Posts : 24
    • Reward points : 0
    • Joined: 2019/12/28 20:45:42
    • Location: East Coast
    • Status: offline
    Re: I2C Stop bit 2020/03/01 19:55:26 (permalink)
    0
    Update.....  I bread-boarded the circuit shown in post #1, connected it to I2C and the PIC32MX.  The circuit worked like a champ!  Programming turned out to be easy also.  Problem solved, at least for me.
     
     
    #4
    Gort2015
    Klaatu Barada Nikto
    • Total Posts : 3835
    • Reward points : 0
    • Joined: 2015/04/30 10:49:57
    • Location: 0
    • Status: offline
    Re: I2C Stop bit 2020/03/01 20:18:12 (permalink)
    0
    I know, it's a good feeling, the latest code you write will be the best ever.

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #5
    robert.galaxy
    CTO
    • Total Posts : 24
    • Reward points : 0
    • Joined: 2019/12/28 20:45:42
    • Location: East Coast
    • Status: offline
    Re: I2C Stop bit 2020/03/02 06:53:58 (permalink)
    0
    Attached is an oscilloscope capture of the STOP bit circuit in action.  Channel 1, top yellow trace, is SCL at 5 volts per division.  The transfer of the last two bytes is shown, and after, the clock signal goes high so the STOP can be signaled.  
     
    Channel 2, the middle magenta trace, is SDA at 2 volts per division. You can see the bits for the last two bytes and the rising edge when SCL is high, which is the STOP.  
     
    Channel 3, the bottom blue trace at 2 volts per division, is the output of the STOP detector, the design of which is shown in an earlier message in this thread.  Note that the SDA signal is rather clean, this is important since that line is used as a rising edge clock on the STOP detection circuit.  As a safeguard, you may want to check  I2CxSTATbits.P as a double check, this bit will be ON if the STOP is valid.
     
    Below is a listing of the interrupts that occur when receiving a message with the STOP circuit functioning.
    mode=0 indicates slave IDLE mode, mode=3 indicates slave message receiving mode.
     
     1 mode=0, I2C2STAT=0x0208 RVC=0x00    the address byte interrupt
     2 mode=3, I2C2STAT=0x0228 RVC=0x02    data bytes arrive
     3 mode=3, I2C2STAT=0x0228 RVC=0x00
     4 mode=3, I2C2STAT=0x0228 RVC=0x08
     5 mode=3, I2C2STAT=0x0228 RVC=0x06
     6 mode=3, I2C2STAT=0x0228 RVC=0x3A
     7 mode=3, I2C2STAT=0x0228 RVC=0x1F
     8 mode=3, I2C2STAT=0x0228 RVC=0x14
     9 mode=3, I2C2STAT=0x0228 RVC=0x14
    10 mode=3, I2C2STAT=0x0228 RVC=0x03
    11 mode=3, I2C2STAT=0x0228 RVC=0x02
    12 mode=3, I2C2STAT=0x0228 RVC=0x05
    13 mode=3, I2C2STAT=0x0228 RVC=0x10
    14 mode=3, I2C2STAT=0x0228 RVC=0x6D
    15 mode=3, I2C2STAT=0x0228 RVC=0x18
    16 mode=3, I2C2STAT=0x0228 RVC=0x01  last data byte arrives
    17 mode=3, I2C2STAT=0x0030                   the STOP interrupt occurs here
     
    this gap in time can be considerable, so arrival of the next address byte is not a reasonable
    signal that the prior message is complete
     
    18 mode=0, I2C2STAT=0x0208 RVC=0x00 the address bye of the next message
    19 mode=3, I2C2STAT=0x0228 RVC=0x02
    20 mode=3, I2C2STAT=0x0228 RVC=0x00
    21 mode=3, I2C2STAT=0x0228 RVC=0x08
     
    Note: the data bytes above do not match the 'scope traces, since the data capture and the oscilloscope could not be easily synchronized.  Also note that the 'scope is not showing the decoded data, since it was set to display only the end of a message, not including the START bit.  Lastly, note that without the external STOP circuit, the listing above would be missing interrupt #17.
     
     
    post edited by robert.galaxy - 2020/03/02 07:05:08

    Attached Image(s)

    #6
    robert.galaxy
    CTO
    • Total Posts : 24
    • Reward points : 0
    • Joined: 2019/12/28 20:45:42
    • Location: East Coast
    • Status: offline
    Re: I2C Stop bit 2020/03/24 04:58:47 (permalink)
    0
    BTW, for anyone planning to use the STOP detection circuit I provided...I found that at RESTART condition can cause a false STOP signal if the SDA signal has a bit of a noisy falling edge.  This is easily prevented by using a Schmidt trigger inverter, in my case I used a 74HC2G14GW-Q100H which conveniently has a second inverter to place in series so the signal can be inverted twice....back to its original polarity.
    #7
    Jump to:
    © 2020 APG vNext Commercial Version 4.5