Harmony V3 Bad SYSCLK Calculation
The configurator calculating wrong SYSCLK.
I cannot get 80Mhz SYSCLK only 72Mhz. The input clk is 8Mhz crystal and I use the standard PLL configuration (DIV_2 and MUL_20), but the configurator allways calculating 72Mhz which is wrong.
Even worse the Clock configurator tool do the same and complains that HS oscillator must be between 10-25 Mhz which is wrong, and don't want to use MUL_20 only MUL_18 which results in 72Mhz.
Is there any reason doing this, or it is a simple bug?