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AnsweredHot!Harmony V3 Bad SYSCLK Calculation

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Codewizards
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2020/02/19 12:11:18 (permalink)
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Harmony V3 Bad SYSCLK Calculation

Hi,
The configurator calculating wrong SYSCLK.
I cannot get 80Mhz SYSCLK only 72Mhz. The input clk is 8Mhz crystal and I use the standard PLL configuration (DIV_2 and MUL_20), but the configurator allways calculating 72Mhz which is wrong.
Even worse the Clock configurator tool do the same and complains that HS oscillator must be between 10-25 Mhz which is wrong, and don't want to use MUL_20 only MUL_18 which results in 72Mhz.
 
Is there any reason doing this, or it is a simple bug?
 
Regards
 
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nigelwright7557
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Re: Harmony V3 Bad SYSCLK Calculation 2020/02/19 15:46:36 (permalink)
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I suspect 72MHz is max frequency of processor hence it wont go any higher.
 
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arpananand
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Re: Harmony V3 Bad SYSCLK Calculation 2020/02/19 19:18:57 (permalink)
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which device are you using?
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Codewizards
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Re: Harmony V3 Bad SYSCLK Calculation 2020/02/20 01:11:15 (permalink)
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Hi,
 
It is a PIC32MX795F512L which is running on 80Mhz max and we use it successfully over many years in multiple products.
Right now I just tried to migrate one of our project into Harmony 3 and start playing with this, and realised tht H3 caps the device speed at 72Mhz whatever I do.
 
Best Regards
 
 
 
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arpananand
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Re: Harmony V3 Bad SYSCLK Calculation 2020/02/20 03:19:38 (permalink) ☼ Best Answerby Codewizards 2020/02/20 03:27:53
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its a bug which will be fixed in next release. for now you can configure multiplier value in  DEVCFG2 device configuration tree structure and proceed. 
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