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Hot!Force SDO output on SPI to low

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dB4301
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2020/02/07 15:14:36 (permalink)
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Force SDO output on SPI to low

I'm hoping this should be very simple, but haven't found the solution yet.
I'm using just the output of an SPI (don't need frame,read, enable etc.), just SDO.
The one thing that does need to happen is to ensure that after the transmit is done, the output defaults to '0'.
The data comes out correctly and at the right rate, but regardless of what I write (even if the last word is zeros) the output keeps switching back to '1'.
I believe I have selected such as CKE = '1' on SPIxCON. I do have ENBUF enabled, but this occurs regardless of ENBUF setting.
MSTEN is '1'. Running 16-bit words. Setup is using Harmony 3. Tried selecting pull-down resistor (and not) from the Harmony environment...no difference.
Any thoughts would be appreciated.
Thanks in advance.
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    jg_ee
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    Re: Force SDO output on SPI to low 2020/02/07 15:53:03 (permalink)
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    Edit: Poor reading comprehension skills
     
    In addition to the CKE bit, you also have the CKP (Clock Polarity Select) bit, which indicates whether the clock is to idle high or idle low. 
     
    You need to make sure the CKP = 0 for idle low.
     
    You then may need to change CKE bit as well since it's operation is referenced to the idle clock level.
    post edited by jg_ee - 2020/02/10 10:04:14
    #2
    Gort2015
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    Re: Force SDO output on SPI to low 2020/02/07 16:20:14 (permalink)
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    SPI uses an exchange protocol.
     
    1. write spi buffer SPIxBUF
    2. wait for SPIxSTAT bit SPIRBF to go high
    3. read spi SPIxBUF
     
    You can use just SDO but SPIxBUF must still be read.
    post edited by Gort2015 - 2020/02/07 19:38:39

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #3
    NorthGuy
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    Re: Force SDO output on SPI to low 2020/02/07 18:44:08 (permalink)
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    You can disable SPI. When it's disabled the SDO pin is controlled by the LAT setting (assuming TRIS is 0).
    #4
    ibbro
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    Re: Force SDO output on SPI to low 2020/02/07 18:58:14 (permalink)
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    I've found that SDO stays at the level of the last bit output. Doesn't matter in my application. Strange that in yours it always goes low. I'm on a PIC32MZ.
     
    #5
    visenri
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    Re: Force SDO output on SPI to low 2020/02/08 06:33:22 (permalink)
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    IIRC, at least with 8 bit devices, after the last clock cycle:
    • With CKE = 0, SDO stays at the level of the last bit output (as already pointed by "ibbro").
    • With CKE = 1, SDO stays at the level of the first bit shifted in through SDI.
    I think some solutions may be:
    • If it fits your application, use CKE = 0 and write a 0 as the last bit.
    • If this is not possible, use CKE = 1 and tie SDI input to 0 (if not using it and you can afford wasting that pin).
    • If none of the above is possible , i would disable SPI and control it's state with LAT register (as already pointed by "NorthGuy"). But in this case you have to wait for transmission to finish before disabling SPI (with 8 bit devices with PPS you can also change pin function to normal pin).
    #6
    dB4301
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    Re: Force SDO output on SPI to low 2020/02/10 13:08:36 (permalink)
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    Hello,
    Thanks for all the suggestions. The link between the SDI and the output is apparently what I was missing.
    This seems to propagate whether SDI is disabled or not, but as NorthGuy mentioned, this could then possibly be controlled by the LAT setting. I enabled the SDI in Harmony specifying that the SDI (though not used) should use a "pull-down" setting on the pin input. That did the trick. Whether this is the best solution is a point of discussion, but it certainly got me over the hump.
    Thank you!
     
    #7
    ThierryV
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    Re: Force SDO output on SPI to low 2020/02/25 07:15:25 (permalink)
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    Hi,
    On my device (PIC32MX370), the idle state of my SDO is random (CKP=1, CKE=0, master mode).
    I send three 0xFF.
    After the last clock of the first data, the SDO stays HIGH.
    After the last clock of the second data, the SDO turns LOW.
    Then after the last clock of the third data, the SDO returns HIGH.
     
    My solution was to disable the SDO line, between each sending, to controls the line with the LAT
    SPI1CONCLR=_SPI1CON_DISSDO_MASK;
    SpiChnWriteC(SPI_CHANNEL1, data);
    while( SpiChnIsBusy(SPI_CHANNEL1) );
    SPI1CONSET=_SPI1CON_DISSDO_MASK;
    #8
    ThierryV
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    Re: Force SDO output on SPI to low 2020/02/25 07:23:06 (permalink)
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    visenri, you're right.
    The SDO idle state is linked to the first bit received on SDI.
    This is valid with CKE = 0, too.
     
     
    post edited by ThierryV - 2020/02/25 07:25:26
    #9
    dB4301
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    Re: Force SDO output on SPI to low 2020/02/25 07:32:09 (permalink)
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    As a point of interest (related to SPI). I had set up a DMA to output a stream of continuous data, but had the disabled SDI ('0' from the pull down) showing up in between the sends. I had the enhanced buffer enabled, which ended up being the source of the problem, when the DMA was directed straight to the output register with no enhanced buffer enabled, the continuous output stream worked fine.
    #10
    ThierryV
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    Re: Force SDO output on SPI to low 2020/02/25 08:00:09 (permalink)
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    On other part of my project, I also use SPI + DMA + Enhanced buffer + DISSDI, and all works fine.
     
    My SPI_Tx is configured to "Half empty" (which trigs the DMA channel), so that the SR register always has data available from its buffer, and there is no gap (idle state) between each bytes.
    #11
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