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henkebenke
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2020/01/24 16:49:30 (permalink)
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About pic32 execution speed

Hi,  I have just made some experiments with IIR filters.  I have put together a 32 bit IIR DF1, and it takes 21 instructions.
Device: pic32MZ0512efe, 200 Mhz
Therefore I expected it to take 21 cycles to complete. I tested it in a loop, so one can expect that all the code is cached from flash - that is, no wait states. But it took 31 cycles.
I read somewhere that this CPU don't have any issues with delays if an instruction loads a register, and the following uses that register. Such as:
 
lw t0, 8(a1)
madd t0, a0
 
But there is indeed a delay there! So I rearranged the loading like this:
lw t0, 0(a1) /*b0*/
mult t0, a2
lw t0, 4(a1)
lw t1, 0(a0)
lw t2, 8(a1)
madd t0, t1
lw t1, 4(a0)
lw t0, 12(a1)
madd t2,t1
lw t1, 8(a0)
lw t2, 16(a1)
madd t0, t1
lw t1, 12(a0)
lw t6, 0(a0)  /* queue updating */
madd t1, t2
sw t6, 4(a0)
lw t6, 8(a0) 
sw a2, 0(a0)
sw t6, 12(a0)
extr_r.w a2, $ac0, 31
sw a2, 8(a0)
 
Now, the whole thing executes in 25 cycles. 
 
Furthermore, the usual way to implement FIR filter is to load a couple (8 or 10) registers, and do five consecutive MADD instructions.  But at least when I single stepped it, it took two cycles to complete each MADD instruction.
Any comments?
 
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    simong123
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    Re: About pic32 execution speed 2020/01/24 18:09:05 (permalink)
    4.5 (2)
    From table 2.2 in the microAptiv software manual (MD00934-2B-microAptivUC-SUM-01.03.pdf) any ext* instruction which is followed by a dependant gpr operation will incur a 3clk delay, so try moving that up.
     
    There is a 0 clk load to use penalty, however that only applies if the data is in the cache.
     
    I have found that hand optimising code on the PIC32 to be a bit of a black art, with lots of trial and error :-)
     
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