• AVR Freaks

Hot!MCP3903 SPI

Author
Luke
New Member
  • Total Posts : 2
  • Reward points : 0
  • Joined: 2020/01/16 20:58:55
  • Location: Victoria, BC, Canada
  • Status: offline
2020/01/18 14:14:07 (permalink)
0

MCP3903 SPI

Hi,
 
I hope this is the right place to post this. If it belongs somewhere else I can move it.
 
I am have a PCB with 3 MCP3903 AFEs which are connected to a CC3200SF Microcontroller. I believe that I have SPI set up properly but I am unable to receive anything from any of the AFEs when I try talking to them, I can't even force them to send me all 0s by giving them the wrong address. I am using Mode 0,0, and I am holding the nRST high.
 
I have attached my scope captures (Sorry I only have 2 probes that share a ground) of what the SPI channels look like at the AFE. I am attempting to read from the CONFIG register (0x0A), following the control byte scheme I am sending 0x55 (((0x0A << 1)|0x01)|0x40) as the control byte followed by 3 0x00s for clock pulses so the MISO can send back data.
"CS SCLK.png" shows my CS is going low for the 4 sets of clock pulses before going high again and repeating the process.
"SCLK MOSI.png" shows that I am sending 0x55 as I expect.
"SCLK MISO.png" shows that my MISO is only ever low.
 
Other things I have tried:
Talking to the other AFEs with the exact same results.
Trying on another PCB.
The Mode is 00, and Mode 11.
The chip is clocked with an 8MHz for the analog.
SPI is running at 1MHz.
Talking to other register addresses, all give the same result.
Checking if MISO and MOSI are the correct way around.
 
I'm pretty much out of ideas at this point and am thankful for any help you can give me.
 
Thanks,
Luke
post edited by Luke - 2020/01/23 19:44:59

Attached Image(s)

#1
Luke
New Member
  • Total Posts : 2
  • Reward points : 0
  • Joined: 2020/01/16 20:58:55
  • Location: Victoria, BC, Canada
  • Status: offline
Re: MCP3903 SPI 2020/01/23 20:02:25 (permalink)
4 (1)
I'll leave this up for anyone who thinks they have done everything only to now find out that they haven't.
 
The AVDD was only at 3V3. I believe the POR is holding the Digital interface in reset. I need to do a lot of surgery to test this but it makes perfect sense.
#2
Jump to:
© 2020 APG vNext Commercial Version 4.5