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Hot!Mismatch between UART2 configuration and SYSCLOCK setting

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yts
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2019/12/26 17:22:40 (permalink)
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Mismatch between UART2 configuration and SYSCLOCK setting

bsp v3.5.0, core v3.5.2, csp v3.5.2, dev_pack v3.5.0, mhc v3.3.4
PIC32MX270F256B-50I/SP

The SYSCLOCK can be successfully set to be 50 MHz by modifying the bsp.py. (see the topic #5 at https://www.microchip.com/forums/m1094799.aspx and the attached figure)

However, the problem arises when I use the uart2 functionality.
MHC3 configures the uart2 functionality as if the PIC works not at 50 MHz but at 48MHz.

In Plib_uart2.c,
 U2BRG = 103;
This setting should be modified as
 U2BRG = 108;

In Plib_uart2.h,  
 #define UART2_FrequencyGet()    (uint32_t)(480000000UL)
This line should be modified as
 #define UART2_FrequencyGet()    (uint32_t)(500000000UL)
 
yts

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    yts
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    Re: Mismatch between UART2 configuration and SYSCLOCK setting 2019/12/26 17:59:07 (permalink)
    5 (1)
    I found the  solution.
     
    Select  MHC->Tools->Clock configuration in the MENU of MPLABX to show the clock diagram window.
    and generate the code once again.
     
    The problem is never solved without showing the clock diagram window.
     
    yts
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