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Hot!Problem with the communication between PIC & SPI EEPROM

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dirfys
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2019/11/16 06:47:25 (permalink)
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Problem with the communication between PIC & SPI EEPROM

I'm using PIC16F1789 and I want to access with SPI protocol an EEPROM 25AA256. I've used the code that is produced by MCC (MPLAB X IDE v5.20) for PIC configuration as well as the suggested code from AN2045 (Interfacing Serial EEPROMs with 8-Bit PIC® Microcontrollers) for the communication with the EEPROM.
The problem that I'm facing is that although the PIC sends data from SDO, it doesn't receive anything from EEPROM at the SDI.
I realized that when I traced with a Logic Analyzer the communication between them.
The attached files are the schematic with the connections between PIC and EEPROM, as well as the tracer from the Logic Analyzer.
The code for the MSSP Initialization is the following:
void Init_MSSP_SPI(void)
{
    TRISBbits.TRISB0 = Output; //Set the RB0 pin (SS or CS) as output
    TRISCbits.TRISC3 = Output; //Set the RC3 pin (SCK) as output
    TRISCbits.TRISC4 = Input; //Set the RC4 pin (SDI) as input
    TRISCbits.TRISC5 = Output; //Set the RC5 pin (SDO) as output
    LATBbits.LATB0 = Enabled; //Activate the Chip Select pin to deselect the SPI Slave
    
    /* SSPEN enabled; WCOL no_collision; CKP Idle:Low, Active:High; SSPM FOSC/4;
     * SSPOV no_overflow;*/
    SSP1CON1 = 0b00100000; /* Write Collision Detect: 0=No collision,
                            * Receive Overflow Indicator: 0=No overflow,
                            * Synchronous Serial Port Enable: 1=Enables serial port
                            * & configures SCK, SDO, SDI and SS as the source
                            * of the serial port pins,
                            * Clock Polarity Select: 0=Idle state for clock is a low level,
                            * Synchronous Serial Port Mode Select: 0000=SPI Master mode,
                            * clock = FOSC/4 */
    
    /*In SPI master mode, this register is not used.*/
// SSP1CON3 = 0b00000000;
    
    /*With the current configuration, this register is not used.*/
// SSP1ADD = 0b00000000; //Baud Rate Clock Divider: 00000000=SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
    
    /* R_nW write_noTX; P stopbit_notdetected; S startbit_notdetected; BF RCinprocess_TXcomplete;
     * SMP End; UA dontupdate; CKE Idle to Active; D_nA lastbyte_address;*/
    SSP1STAT = 0b10000000; /* SPI Data Input Sample: 1=Input data sampled at end of data output time,
                            * SPI Clock Edge Select: 0=Transmit occurs on transition from Idle to active clock state,
                            * xxxxx: 00000,
                            * Buffer Full Status: 0=Receive not complete, SSPBUF is empty */
    
    
} //End of Init_MSSP_SPI()

 
while for the EEPROM access is:

 
uint8_t writeBuffer[] = {0x1A, 0x2A, 0x4A, 0x8A};
uint8_t readBuffer[10];
uint8_t addressOfBuffer[] = {0x00, 0xAB, 0x10};
uint8_t readOneByte;
 
 
 
uint8_t EEPROM_Read1Byte(uint8_t *addressBuffer, uint8_t addrLen)
{
uint8_t ReadByte;


//Select the EEPROM chip
EEPROM_CS = Disabled;


//Send Read Command
SPI_ReadWrite1byte(EEPROM_READ_DATA);

//Send address byte/s
SPI_ReadWriteBytes(addressBuffer, addrLen, NULL);

//Send Dummy data to clock out data byte from slave.
ReadByte = SPI_ReadWrite1byte(DUMMY_DATA);


//Toggle CS line to end operation
EEPROM_CS = Enabled;


//Return data byte read
return(ReadByte);

} //End of function "EEPROM_Read1Byte"
 

/******************/
readOneByte = EEPROM_Read1Byte(addressOfBuffer,sizeof(addressOfBuffer)); //Reads one byte of data from the address specified.

As you can see from the tracers, the EEPROM doesn't respond back to the PIC. Although I have nothing written at this memory address, I would expect to read garbages.
Thus, my question is why do I see this behavior? What could be wrong in my configuration (wiring and code) that causes this behavior?
post edited by dirfys - 2019/11/16 06:49:16

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#1

4 Replies Related Threads

    rodims
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    Re: Problem with the communication between PIC & SPI EEPROM 2019/11/16 10:40:27 (permalink)
    5 (1)

    As you can see from the tracers, the EEPROM doesn't respond back to the PIC. Although I have nothing written at this memory address, I would expect to read garbages.

    If you never have written to the EEPROM you usually should expect 0xff in all memory locations (same after ERASE), but definitely no "garbage". For testing I would add a pullup for the SO (MISO) line.  It is not really required, but it should help to interpret the SO line, when CS is not active (SO line floating).
    If your EEPROM would really contain 0x00 in your addressed memory locations, then you now would see the level changing. However, if the EEPROM still does not respond (e.g. damaged or never really selected), then the SO line will be always high. In this case you still don't know whether the EEPROM responds.
     
    Concerning the reading the SPI with your PIC, you should set
      ANSELC bit 4 correctly to make that input digital. (see manual)
    for your
    TRISCbits.TRISC4 = Input; //Set the RC4 pin (SDI) as input

    Not sure whether it is required, but with that you are on the safe side.
     
    But before dealing with the PIC input I would focus on the Salea Logic Analyzer output.
    The PIC input simply adds complexity for the moment, which you should postpone.
    For me the Logic analyzer output does not fit to your code. I assume those two clips should demonstrate the same read access ? I do not see the end of the CS going inactive again. And the Salea is not "active" (Demo Mode displayed) so you have loaded this trace (or both separately) from disk ?
     
    From the manual
    The device is selected by pulling CS low. The 8-bitREAD instruction is transmitted to the 25XX256followed by the 16-bit address, with the first MSB of theaddress being a “don’t care” bit.

    The EEPROM is 32 KB which ist 256 Kbit. You are using a 24 bit address, but the device expects a 16 bit address.
    But  even then your traces show a sequence of   0x03, 0xAB ,  0x00, 0x10, 0x00, which for me does not fit to your code. 
    May be you first fix the length of the address and make a new trace which shows the complete access from CS going low back to CS going High again.
     
    post edited by rodims - 2019/11/16 10:41:33
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    dirfys
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    Re: Problem with the communication between PIC & SPI EEPROM 2019/11/16 16:27:00 (permalink)
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    The "garbages" is a matter of interpretation. Either the value is 0xFF or whatever else, if we don't need it, it's a garbage. Smile: Smile
    Anyway, I found the solution in this problem. When I set CKP=1 (Idle state for clock is a high level), the EEPROM responded back to the PIC.
    But to be honest, I haven't understood how this value affects the functionality of the EEPROM. What I have found from the datasheet of 25AA256 EEPROM is: "Data (SI) is sampled on the first rising edge of SCK after CS goes low.", as well as the SI & SO timing (see attached pictures). But I can't understand if and how it's related to CKP.

    Attached Image(s)

    #3
    Jerry Messina
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    Re: Problem with the communication between PIC & SPI EEPROM 2019/11/17 05:06:46 (permalink)
    5 (1)
    SPI has different modes of operation... clock idle state, when data is valid, etc.
    See https://en.wikipedia.org/wiki/Serial_Peripheral_Interface for a discussion of these.
     
    You don't seem to have MCC setup to follow the recommendations in AN2045 for SPI mode (0, 0)
     
    #4
    NKurzman
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    Re: Problem with the communication between PIC & SPI EEPROM 2019/11/17 08:41:14 (permalink)
    5 (1)
    The "garbages" is a matter of interpretation.
    Which is exactly why you should never use it in a post. It provides no useful information in this context.

    Note: SPI always responds if it’s chip select is low.
    post edited by NKurzman - 2019/11/17 08:42:47
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