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Hot!EEPROM on PIC18

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Author
ric
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Re: EEPROM on PIC18 2019/11/06 14:27:15 (permalink)
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FSR -> SFR :)

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#21
mbrowning
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Re: EEPROM on PIC18 2019/11/06 14:39:35 (permalink)
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jtemples
 
EE_Key_x are in access bank and loaded with 0x55/0xaa from a message (to prevent a bad message from corrupting flash).

 
They pass 55/AA in every "write" message?

Every one.
// *****************************************************************************
// Write Flash
//        Cmd     Length----- Keys------   Address---------------  Data ---------
// In:   [<0x02> <0x00><0x00><0x55><0xAA> <0x00><0x00><0x00><0x00> <Data>..<data>]
// OUT:  [<0x02> <0x00><0x00><0x00><0x00> <0x00><0x00><0x00><0x00> <0x01>]
// *****************************************************************************


Go Navy! Beat Army!
#22
jtemples
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Re: EEPROM on PIC18 2019/11/06 15:41:14 (permalink)
+1 (1)
There's no checksum?  If any of the address or data bytes are corrupted, that's ok?
#23
crosland
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Re: EEPROM on PIC18 2019/11/07 03:05:14 (permalink)
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mad_c
crosland
Simple question: Is XC8 (I'm currently using 2.10) guaranteed to generate the correct unlock sequence for EEPROM writes?


Hi,
 
A list of registers that might be associated with unlock sequences is stored with the compiler. Any access to these registers must be done without extraneous bank selection instructions appearing in the sequence. You can see the addresses of these registers in the INI for the device you are using, in <dist>/pic/dat/ini/18f26k42.ini, for example. Look for VOLSFRS.
 
If the compiler is not producing the correct sequence for an SFR on this list, this is a compiler bug. If a register used in an unlock sequence is not on the list, then it needs to be added. In both cases, contact Support with the relevant information.
 
Jeff.




Thank you :)
#24
1and0
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Re: EEPROM on PIC18 2019/11/07 05:42:30 (permalink)
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mad_c
A list of registers that might be associated with unlock sequences is stored with the compiler. Any access to these registers must be done without extraneous bank selection instructions appearing in the sequence. You can see the addresses of these registers in the INI for the device you are using, in <dist>/pic/dat/ini/18f26k42.ini, for example. Look for VOLSFRS.
 

Quoted from the INI file:
 
#   VOLSFRS=<range_start>-<range_end>,...
#           Instructions generated by the compiler that access SFRs in the given memory
#           ranges will won't be optimized by the assembly optimizer
#25
NKurzman
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Re: EEPROM on PIC18 2019/11/07 06:03:19 (permalink)
+1 (1)
There it is. You have the Jeff guarantee.
They specifically code for it.
#26
JPortici
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Re: EEPROM on PIC18 2019/11/07 07:16:59 (permalink)
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ric
FSR -> SFR :)


VOLSFRS, maybe it's VOL(something) SFRs (last s as in plural :D)
#27
1and0
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Re: EEPROM on PIC18 2019/11/07 07:53:06 (permalink)
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Just curious, are there any Special Function RegisterS that are not VOLatile?
 
#28
du00000001
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Re: EEPROM on PIC18 2019/11/07 10:47:42 (permalink)
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1and0
Just curious, are there any Special Function RegisterS that are not VOLatile?

 
All the config registers (think of BRRs, SPI, I2C and alike) are SFRs, but not necessarily volatile.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
#29
1and0
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Re: EEPROM on PIC18 2019/11/07 11:04:32 (permalink)
+1 (1)
du00000001
1and0
Just curious, are there any Special Function RegisterS that are not VOLatile?

All the config registers (think of BRRs, SPI, I2C and alike) are SFRs, but not necessarily volatile.

Like these ;)
extern volatile unsigned char   SSP1BUF __at(0xF92);
extern volatile unsigned char   SSP1ADD __at(0xF93);
extern volatile unsigned char   SSP1MSK __at(0xF94);
extern volatile unsigned char   SSP1STAT __at(0xF95);
extern volatile unsigned char   SSP1CON1 __at(0xF96);
extern volatile unsigned char   SSP1CON2 __at(0xF97);
extern volatile unsigned char   SSP1CON3 __at(0xF98);

 
 
#30
crosland
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Re: EEPROM on PIC18 2019/11/08 08:08:31 (permalink)
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1and0
Just curious, are there any Special Function RegisterS that are not VOLatile?

 
I would argue they should all be volatile. Otherwise you would need to start hacking the provided headers (or write your own) when you need to share an SFR between, say, interrupts and main context.
#31
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