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Hot!Calibrate Oscilloscope

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Speedi
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Re: Calibrate Oscilloscope 2019/11/05 04:24:26 (permalink)
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1and0
 
No, it is incomprehensible, but since you all have told me certain things now, I thought in bed last night that it might be the frequency gain which I will be looking at later today. Can't see what else it should be, will not assume that there is error in MPLAB's update which causes it, and has not changed my code, but has made frequency changes, switched the crystal from 4Mhz to 16Mhz, and the only thing I haven't testet is the gain.
 
Otherwise, I'll try with blank startup while considering second and better PIC :)
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Mysil
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Re: Calibrate Oscilloscope 2019/11/05 06:21:48 (permalink)
+1 (1)
Hi,
You did say in message #14 that you now have PIC16F1713-I/SP and PIC18F23K20-I/SP.
You may use either of these devices in a solderless breadboard with 2.54 mm spacing.
 
Both devices have the same Master mode I2C peripheral.
Example code and comments in message #16 were intended for these devices.
Registers may be named SSPCON1 or SSP1CON1  depending on device type,
device hardware support file that is included with #include <xc.h> have definition of those symbols.
For some families, both definitions are available.
 
C compiler will understand binary constants, decimal constants and hexadecimal constants,
so 0b1000, 0x8 and 8 (decimal integer) are all the same.
    0b1011 , 0xB or 11 are also the same when translated by the compiler. I2C Firmware Controlled Master mode (slave IDLE), is also available in PIC18F23K20 and PIC16F1713,
and means that your program must bitbang the signals for Master mode transfer.
 
    Mysil
 
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davea
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Re: Calibrate Oscilloscope 2019/11/05 08:06:57 (permalink)
+1 (1)
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or sending
a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter
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Speedi
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Re: Calibrate Oscilloscope 2019/11/05 08:15:46 (permalink)
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Mysil
 
PIC16F1713-I / SP was an LF but just got a look and I also have a PIC16F1713-I / SP. So the choice stands between the two for now :)
 
For something like this, I make my own print but use the socket for ic. Takes a little longer, but more stable and better to deal with.
 
Will spend the evening to see which one I take, think it will be 1617 (y)
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Speedi
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Re: Calibrate Oscilloscope 2019/11/05 08:18:26 (permalink)
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devea
 
And that is why I assumed it should also be activated so that the master could register this, but understood (y)
 
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Speedi
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Re: Calibrate Oscilloscope 2019/11/05 08:24:35 (permalink)
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Looked at the frequency gain which was only 1.42V and the datasheet writes about 4-5.5V but no change with more gain, and also examined if a frequency could be read on a port set as "TRISBbits.TRISB5 = ~ TRISBbits.TRISB5;" and the measuring was around 11MHz so it fluctuates even at 1.42V :-/
 
The code then :(
#26
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