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Helpful ReplyHot!I2C Slave - how to detect when the Master has completed a write operation?

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allenhuffman
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2019/10/29 12:11:55 (permalink)
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I2C Slave - how to detect when the Master has completed a write operation?

I have been looking at the data sheet for 24FJ128GA202 trying to see if there is something in I2CxSTAT or other registers that might let me know when the Master has done a write. When I view the I2C traffic on a scope, the I2C parser correctly identifies the bytes in the write operation, and I am trying to do that in software.
 
I am using the I2C IRQ and want to know when all the bytes have been received from arbitrary-sized messages.
 
 
For example, on Arduino I2C, there is an available() function. The Master might do something like:
 
start()
write()
write()
...
write()
stop()
 
And on the Slave, you can sit in a loop checking for data:
 
while available()
   read()
 
If you read 127 bytes, and only 5 were written, you get the 5 back. It works very much like dealing with a pipe or serial port buffer. I am trying to create this for the PIC24s we are using. (We use the CCS compiler, and it does not seem to have an API call for this.)
post edited by allenhuffman - 2019/10/29 12:14:18
#1
ric
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/29 12:13:07 (permalink)
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Are you detecting STOP cycles?
 

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allenhuffman
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/29 12:17:28 (permalink)
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ricAre you detecting STOP cycles?

 
I looked into the P and S status bits, but they seem to occur for each byte rather than the end of the transmission.

Allen C. Huffman, Sub-Etha Software (est. 1990) www.subethasoftware.com
Embedded C, Arduino, ESP8266/32, BASIC Stamp and PIC programmer.
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ric
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/29 12:22:08 (permalink) ☄ Helpfulby allenhuffman 2019/10/29 13:43:38
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That is not correct.
The S bit will be set for the entire transaction, and P clear, then this will swap after the STOP is received.
Some PICs are able to interrupt after START and STOP cycles.
 

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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/29 13:02:18 (permalink)
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Interesting. I enabled it, and in my ISR I did a counter. I wrote 10 bytes (form a C# program on a PC using an FTDI I2C interface) and the counter climbed to 10. I was checking the bit in the ISR.
 
I will re-examine what I did.

Allen C. Huffman, Sub-Etha Software (est. 1990) www.subethasoftware.com
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ric
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/29 13:59:26 (permalink)
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I've not used that FTDI chip, but it sounds like it has done ten individual transactions, each one surrounded by START and STOP states.
I assume you can't change your protocol to put a length count at the start, or add some sort of terminating character.
 

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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/30 07:53:55 (permalink)
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We use a variety of PIC24 chips in our system. The board I have hooked up at the moment is 24FJ128GA202.
 
Should I be able to read the S and P status bits without interrupts enabled for them?
 
Edit: I redid my tests today. In the CCS compiler, I am setting up access like this:
 
// I2C2CONH - PCIE enable/disable bit
#word I2C2CONH = getenv("SFR:I2C2CONH")
#bit PCIE = I2C2CONH.6 // bit 6 - enable/disable IRQ on start
#bit SCIE = I2C2CONH.5 // bi5 5 - enable/disable IRQ on stop

// IC2CSTAT - sto(P) and (S)tart bits for status.
#word I2C2STAT = getenv("SFR:I2C2STAT")
#bit P = I2C2STAT.4 // bit 4 - stop
#bit S = I2C2STAT.3 // bit 3 - start

 
I was always getting 1 back from P and S (without the PCIE and SCIE interrupts enabled). I enabled them (like I did in my original testing last week).  In the debugger, I can look at the SFRs and see the bits enabled. but it looks like bit 3 and 4 of the STAT register are always 1.
 
I should note that my whole experiment has been to write some generic I2C code to test what appears to be a hardware flaw in the I2C of some PIC24 chips we have. We have had situations where having one plugged up to the I2C bus will cause a hang if the I2C is enabled (with no code processing anything). Same part with I2C disabled lets everything run. I've been looking into this to try to get a clean, simple sample for the folks at CCS to look at (in case it's something in the library code) or Microchip (if it turns out to be something odd in this particular PIC).
 
post edited by allenhuffman - 2019/10/30 08:41:37

Allen C. Huffman, Sub-Etha Software (est. 1990) www.subethasoftware.com
Embedded C, Arduino, ESP8266/32, BASIC Stamp and PIC programmer.
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Mysil
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/30 09:52:04 (permalink)
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Hi,
You may read the S and P status bits at any time, in ISR, or in main code.
If the I2C peripheral have been just initialized, and no traffic have occurred,
then both S and P will be zero.
When a package have passed, S and P bits will have opposite values. If S bit == 1, then bus is occupied.
If P bit is 1, then bus is free to use.
 
Note that S bit == 1, do not indicate that the local device is involved in communication,
there may be other devices on the bus that are active. 
 
I2C is a communication protocol that depend on correct software supporting the hardware peripheral.
Bad software is more likely to be cause of problems, than differences in hardware.
I2C hardware in PIC24 devices, is mostly very similar, and I2C in 24FJ128GA202 is identical to most other PIC24 and dsPIC33 devices.
 
Are you saying that bits 3 and 4 in one of the registers I2C1STAT, or I2C2STAT, are both 1 at the same time?
if that is the case, then there is something wrong.
 
    Mysil
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allenhuffman
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/10/30 10:10:08 (permalink)
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MysilAre you saying that bits 3 and 4 in one of the registers I2C1STAT, or I2C2STAT, are both 1 at the same time?
if that is the case, then there is something wrong.

 
I agree :-)  Fortunately, there is no shortage of PIC hardware here so I am now working on a different chip and board. Perhaps we got a bad batch of this particular PIC24.
 
Once I get this working, I'll share my results. I have read enough that I believe it should work. I just have to find hardware that works :)

Allen C. Huffman, Sub-Etha Software (est. 1990) www.subethasoftware.com
Embedded C, Arduino, ESP8266/32, BASIC Stamp and PIC programmer.
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allenhuffman
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/11/12 21:50:31 (permalink)
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Are you the same Ric that went through this back in 2003? I found lots of posts, now that I know what to search for (i2c slave stop).
 
I am trying to implement a simple Slave read/respond without interrupts. I read one post that claimed the P isn’t set quickly so it might be missed. I’m just trying to figure out logic to know when I should be checking for P. I am using the CCS compiler and their library calls to init the hardware, get state, and read/write bytes. I’m just having to poll the IRQ bit and P, I think.

Allen C. Huffman, Sub-Etha Software (est. 1990) www.subethasoftware.com
Embedded C, Arduino, ESP8266/32, BASIC Stamp and PIC programmer.
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ric
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Re: I2C Slave - how to detect when the Master has completed a write operation? 2019/11/12 22:07:07 (permalink)
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allenhuffman
Are you the same Ric that went through this back in 2003? I found lots of posts, now that I know what to search for (i2c slave stop).

More than likely. I've been around since this forum was a shiny new toy that had a completely different set of problems to the current forum software! ;)
Do you have a link to one of these 2003 topics? My memory banks overflowed many years ago.
 

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