• AVR Freaks

Hot!ADC rate rejected by MCC (PIC33CK)

Author
Cyber
New Member
  • Total Posts : 25
  • Reward points : 0
  • Joined: 2007/07/02 10:48:55
  • Location: 0
  • Status: offline
2019/10/28 03:43:32 (permalink)
0

ADC rate rejected by MCC (PIC33CK)

I am setting up the shared core ADC to sample four analogue inputs.  MCC provides a warning: "The clock settings must be selected to provide a Core Clock Period more than 14.3ns".  Reading the errata, this comes down to the source clock, a divider shared by all ADC cores and one for each individual core.  Regardless of settings, I cannot get this warning to go away and if I run it, the ADC is not providing meaningful data.
 
14.3ns equates to 70MHz and even if I set FOSC/2 (which is the selected source) to far less, the warning persists, which should be impossible.  Further, the core time selection bits (SHRSAMC) calculated by MCC, which set the sample time, appear to work in reverse.  If I increase any of the dividers, SHRSAMC also increases.  Unless I'm missing something, it should decrease.  This means that by trying to reduce TADCORE, SHRSAMC becomes so large that MCC rejects this too.
 
Any advice?  Is this an MCC bug?
#1

0 Replies Related Threads

    Jump to:
    © 2020 APG vNext Commercial Version 4.5