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Hot!ADC rate rejected by MCC (PIC33CK)

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Cyber
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2019/10/28 03:43:32 (permalink)
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ADC rate rejected by MCC (PIC33CK)

I am setting up the shared core ADC to sample four analogue inputs.  MCC provides a warning: "The clock settings must be selected to provide a Core Clock Period more than 14.3ns".  Reading the errata, this comes down to the source clock, a divider shared by all ADC cores and one for each individual core.  Regardless of settings, I cannot get this warning to go away and if I run it, the ADC is not providing meaningful data.
 
14.3ns equates to 70MHz and even if I set FOSC/2 (which is the selected source) to far less, the warning persists, which should be impossible.  Further, the core time selection bits (SHRSAMC) calculated by MCC, which set the sample time, appear to work in reverse.  If I increase any of the dividers, SHRSAMC also increases.  Unless I'm missing something, it should decrease.  This means that by trying to reduce TADCORE, SHRSAMC becomes so large that MCC rejects this too.
 
Any advice?  Is this an MCC bug?
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    _dex
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    Re: ADC rate rejected by MCC (PIC33CK) 2020/04/16 06:25:47 (permalink)
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    Hi, did you found the solution? I have MPLABX 5.35 and 33CK pic and same similar problem with ADC.
    Actually, is the MCC warning message correct?
    Should not be "period shorter or smaller" than as they writing "more than 14.3ns" ?
     
    I do not understand it. Is the problem because of the system clock is to fast or to small?, sounds like a nonsense.
     
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    Cyber
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    Re: ADC rate rejected by MCC (PIC33CK) 2020/04/16 06:49:22 (permalink)
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    Hi Dex.  The text that says the period should be more than 14.3ns is correct, I believe, and matches what the datasheet says.  There is a formula in the datasheet that explains how the Core Clock speed is a function of the source clock and ADC clock divider.  But the implementation of that equation in MCC appears incorrect, so when you change the source clock or ADC divider to increase the Core Clock speed, MCC calculates the inverse and gets a decreased Clock Speed and prints the error.
     
    I don't think they've fixed the error yet.  What I did was to do the math myself to get the source clock and ADC clock divider that gives me the ADC timing I want, set those values in the ADC registers tab in MCC and ignore the errors.  That worked for me.
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