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Hot!Programming/Verify complete but target device not ready for debugging

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JustRob
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2019/10/18 11:55:37 (permalink)
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Programming/Verify complete but target device not ready for debugging

I'm using the pic18lf47k42 with mplabx ide v5.15 and the xc8 compiler version 2.05
 
When I try to enter the debug mode I get the following error:
Programming/Verify complete
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.
 
Here is my configuration code:
// PIC18F47K42 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1L
#pragma config FEXTOSC = OFF // Oscillator not enabled
#pragma config RSTOSC = HFINTOSC_64MHZ// Reset Oscillator Selection (HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1)

// CONFIG1H
#pragma config CLKOUTEN = ON // Clock out Enable bit (CLKOUT function is enabled)
#pragma config PR1WAY = ON // PRLOCKED One-Way Set Enable bit (PRLOCK bit can be cleared and set only once)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)

// CONFIG2L
#pragma config MCLRE = EXTMCLR // MCLR Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR )
#pragma config PWRTS = PWRT_OFF // Power-up timer selection bits (PWRT is disabled)
#pragma config MVECEN = ON // Multi-vector enable bit (Multi-vector enabled, Vector table used for interrupts)
#pragma config IVT1WAY = ON // IVTLOCK bit One-way set enable bit (IVTLOCK bit can be cleared and set only once)
#pragma config LPBOREN = OFF // Low Power BOR Enable bit (ULPBOR disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

// CONFIG2H
#pragma config BORV = VBOR_2P7 // Brown-out Reset Voltage Selection bits (Brown-out Reset Voltage (VBOR) set to 2.7V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config DEBUG = OFF // Debugger Enable bit (Background debugger disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period selection bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT enabled regardless of sleep)

// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4L
#pragma config BBSIZE = BBSIZE_512// Boot Block Size selection bits (Boot Block size is 512 words)
#pragma config BBEN = OFF // Boot Block enable bit (Boot block disabled)
#pragma config SAFEN = OFF // Storage Area Flash enable bit (SAF disabled)
#pragma config WRTAPP = OFF // Application Block write protection bit (Application Block not write protected)

// CONFIG4H
#pragma config WRTB = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTC = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config WRTSAF = OFF // SAF Write protection bit (SAF not Write Protected)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)

// CONFIG5L
#pragma config CP = OFF // PFM and Data EEPROM Code Protection bit (PFM and Data EEPROM code protection disabled)


 
This code worked for another circuit board.  I'm not seeing where it is configured wrong.
#1

7 Replies Related Threads

    KTrenholm
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 12:55:08 (permalink)
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    You say these settings worked for another board, so have you confirmed your oscillator is connected properly and oscillating on the non-working board?
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    JustRob
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 13:07:51 (permalink)
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    I meant to mention I want to use the internal 64 or 32MHz oscillator.  I thought I was configuring it for the internal oscillator.
    #3
    KTrenholm
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 13:16:25 (permalink)
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    Ah, I probably should have actually looked at the config settings.  I don't know much about PIC18, but I imagine you'd want to turn off CLKOUTEN and CNWEN since you won't be using either of those on the internal oscillator. 
    I'm also not sure what the setting of MCLRE = EXTMCLR is.  Someone more knowledgeable about this micro may know.
     
    Was the other board that these settings worked on the same design?  Or a different design using the same PIC?
    If it's the same design and that one worked and this one doesn't you may need to check the hardware.  Are ICSPCLK and ICSPDAT continuous to the pins of the PIC?  If it's a different design, do you have a circuit diagram of how your programming pins (ICSPCLK/ICSPDAT/MCLR) are connected?
    post edited by KTrenholm - 2019/10/18 13:22:20
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    JustRob
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 13:40:41 (permalink)
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    It is pretty much the same design and the same layout.
     
    Yes, the ICD3 comm lines are attached.  I think where it recognizes the pic and programs it confirms the ICD3 is connected correctly.
     
    I shut off the CLOCKOUTEN and CSWEN and it still won't debug.
     
    I don't see anything for the PGC/PGD settings.
     
     

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    NorthGuy
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 15:17:10 (permalink)
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    I would check if your PIC can run at all. Just insert a blinking LED into your existing app and run it without debugger. If it runs, then you should look at the debugger. If it doesn't run, you need to figure out why.
    #6
    newfound
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 16:39:23 (permalink)
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    #pragma config DEBUG = OFF // Debugger Enable bit (Background debugger disabled)
     
    I thought DEBUG was not meant to be included in the config word settings and left to the debugger to handle as required. Still, I doubt this is the cause of the problem as the debugger should override this setting. Not sure, not my area of expertise...
    #7
    mbrowning
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    Re: Programming/Verify complete but target device not ready for debugging 2019/10/18 16:58:30 (permalink)
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    I always put DEBUG =OFF just for completeness and debug works fine because the bit gets overridden by the IDE/compiler. I’ve never had any problem with debug and PK3. I use 56k42 mostly.

    Is there any connection to the icsp signals other than ICD3?

    Go Navy! Beat Army!
    #8
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