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EngSam
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# dspic33 QEI module : INTDIV and QFDIV

I have working with QEI module for sometime (dspic33ep) , but today is the first time i use a high resolution encoder : 32768 line per rev. which will yield in total count of 131072 at 4x mode. my motor max speed is <1500 RPM

INTDIV:
from FRM of QEI page 6: for INTDIV selection : "The selected clock rate should be at least twice the expected maximum quadrature rate"
I assume the word : "quadrature rate" means the frequency of the A or B signal ?
So calculate F(A/B) = linecount x RPM /60 = 32678 x 1500 /60 = 819 Khz . So for Fcy=60mips we should use a prescale of 32 which leads to 60/32= 1.875 mhz > ( 2* 819 Khz ) . So i used this number , but the system lose steps at speeds above 900 RPM . only when i set the pre-scaler to 16 it worked correctly . so why the QEI needed 60/16= 3.75 mhz >( 4*819 Khz )?

So my Question :
1) is my calculation correct ? what is the issue ?
2) is there a reason not to set pre-scaler to 1 and work at maximum speed all the time no matter what is the encoder resolution ?

I will leave my question on QFDIV , until someone answer this one first , since i do not want to make the thread longer :(
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du00000001
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Re: dspic33 QEI module : INTDIV and QFDIV 2019/10/17 07:32:44 (permalink)
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EngSam
"The selected clock rate should be at least twice the expected maximum quadrature rate"

I'd interpret "quadrature rate" as "count rate" - four times the max. frequency of A resp. B.
But even interpreting the "quadrature rate" as the max. rate of change of A resp. B, this would make it twice the max. frequency of these. Which seems to comply with your findings.

As for you second question: other than - maybe - preserving some energy, I can only see 1 reason for prescaling the clock: debouncing the input signal somewhat better. Beyond this, the input clock shouldn't be of relevance for the QEI.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
EngSam
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Re: dspic33 QEI module : INTDIV and QFDIV 2019/10/17 11:26:19 (permalink)
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thanks for the reply . Although i might not agree about the de-bouncing input , since there is the an input digital filter with separate clock source especially for that which brings me to the second question i had: QFDIV ( filter prescaler ) !!

Again since English is not my native language i have hard time understanding the following quote :
" the filtered output signals can change only after an input level has the same value for three consecutive rising clock edges " ,
The way i understand this : when signal A is HIGH , 3 clock cycles should should happen at least. Then for a full period on Signal A , 6 clocks will pass . then the frequency required by the filter should be > 6* the frequency on A or B . which means > 6*819Khz = 4.9Mhz. then QFDIV should be 8 : since 60/8 =7.5mhz

can you confirm that my assumption is correct ???

EngSam
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Re: dspic33 QEI module : INTDIV and QFDIV 2019/10/17 11:27:34 (permalink)
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https://imgur.com/oi0pBtH link for image showing the the block diagram of the digital filter
du00000001
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Re: dspic33 QEI module : INTDIV and QFDIV 2019/10/17 12:24:47 (permalink) ☄ Helpfulby EngSam 2019/10/18 04:17:27
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OK - might be the QEI requires the 4 clock cycles just for its internal operation ...

Re input filtering:
It's not 3, but the ubiquitous 4 clock cycles!
If you look somewhat closer, you can see the 3 D-FFs feeding the logic gates - - - plus a 4th D-FF forwarding the result."...at least 3 consecutive ..." to feed the logic gates, another one to transfer the result from the gates' output. Not absolutely sure you'll have the QEI counting if you have exactly 3 rising clock edges per input edge...
(I expect this to be basically the same circuit as e.g. in the input signal path of some timers.)

Your basic understanding seems to be ok - I'm just arguing about the number of edges required for stable and reliable operation.

BTW: my mother tongue isn't English either.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)