Re: dspic33 QEI module : INTDIV and QFDIV
☄ Helpfulby EngSam 2019/10/18 04:17:27
OK - might be the QEI requires the 4 clock cycles just for its internal operation ...
Re input filtering:
It's not 3, but the ubiquitous 4 clock cycles!
If you look somewhat closer, you can see the 3 D-FFs feeding the logic gates - - - plus a 4th D-FF forwarding the result."...at least 3 consecutive ..." to feed the logic gates, another one to transfer the result from the gates' output. Not absolutely sure you'll have the QEI counting if you have exactly 3 rising clock edges per input edge...
(I expect this to be basically the same circuit as e.g. in the input signal path of some timers.)
Your basic understanding seems to be ok - I'm just arguing about the number of edges required for stable and reliable operation.
BTW: my mother tongue isn't English either.
PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)