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Hot!PIC18F24K42 MOVFF instruction.

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peterg1000
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2019/10/15 09:40:18 (permalink)
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PIC18F24K42 MOVFF instruction.

Hi,
I've been debugging assembler code for the 18F24K42 processor, and it would appear that the MOVFF instruction fails even though the source and destination registers are in the SFR area (specifically PRODH and PRODL  and access RAM).
Debugging was done using MPLAB X Rev 5.20 with no interrupts executing.
Replacing the instruction "movff SFR,REG" with "movf SFR,w "followed by "movwf  REG" operates as expected, all the registers concerned being in access RAM. Setting the BSR has no effect on the symptoms.
I haven't explored other SFR's other than some of the FSR's, and they too all appear to have the same problem. Maybe its a problem with SFR's that have shadow registers associated with them - again not explored that possibility.
#1

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    mbrowning
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 09:46:04 (permalink)
    +1 (1)
    Note that MOVFF only has a 12bit address, so can only access up to 0x0fff. SFRs are all well above that limit.
     
    You need to use the 3word version MOVFFL which has the full 14bit range.

    Go Navy! Beat Army!
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    Antipodean
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 09:58:52 (permalink)
    +1 (1)
    peterg1000
    Hi,
    I've been debugging assembler code for the 18F24K42 processor, and it would appear that the MOVFF instruction fails even though the source and destination registers are in the SFR area (specifically PRODH and PRODL  and access RAM).
    Debugging was done using MPLAB X Rev 5.20 with no interrupts executing.
     



    IIRC there was an errata for MOVFF that involved interrupts, and the debugger uses an interrupt, even if your code doesn't.
     
    What happens if you set things up, then set a break point a couple of instructions after the MOVFF and look at the register contents.
     

    Do not use my alias in your message body when replying, your message will disappear ...

    Alan
    #3
    1and0
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 10:05:38 (permalink)
    +1 (1)
    As mbrowning said, MOVFF can access only Banks 0 to 15.  All the SFRs in the PIC18 K42 are located in higher banks.  IMO, the K42 cripples the MOVFF instruction.
     
    post edited by 1and0 - 2019/10/15 10:11:04
    #4
    NorthGuy
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 10:12:55 (permalink)
    +1 (1)
    1and0
    IMO, the K42 cripples the MOVFF instruction.


    Yes, that was a very strange change they made. They should've included all the SFRs into the MOVFF range. But it's very typical of PIC18 development. That's why I prefer PIC16.
    #5
    1and0
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 10:24:16 (permalink)
    +2 (2)
    NorthGuy
    Yes, that was a very strange change they made. They should've included all the SFRs into the MOVFF range. But it's very typical of PIC18 development. That's why I prefer PIC16.

    I think it is a design flaw, just like the first enhanced PIC16F1xxx where PORTx, TRISx, and LATx are located in different banks. In these devices, PORTx and LATx cannot be accessed consecutively:
      btfss  PORTB,0
      bcf     LATC,0

    In the newer enhanced PIC16F1xxxx, PORTx, TRISx, and LATx are located in the same bank.
    #6
    peterg1000
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 12:04:35 (permalink)
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    Hi,
    Thanks guys for the words of wisdom - I appreciate the problem now.  Only recently upgraded to use the 24K42 - and what a pain that is in other areas as well!!  The I2C comms (in assembler) were really a pain in the backside compared to the earlier processors I've used - had to scrap and rewrite my routines in their entirety
    I hadn't realised that MOVFFL had been snuck in to the instruction list. The fact that it uses 3 cycles rather than the 2 for discrete instructions when using access RAM sort of negates any advantage IMHO.
    Anyway, thanks again for the guidance - appreciated.
     
    Peter
     
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    1and0
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    Re: PIC18F24K42 MOVFF instruction. 2019/10/15 13:03:36 (permalink)
    +1 (1)
    peterg1000
     
    I hadn't realised that MOVFFL had been snuck in to the instruction list. The fact that it uses 3 cycles rather than the 2 for discrete instructions when using access RAM sort of negates any advantage IMHO.
     

    Yeap!  You have two choices:
    • use MOVF/MOVWF for Access RAM and alter the WREG register, or
    • use MOVFFL at the expense of one more instruction word and cycle.
    #8
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