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Hot!How to work dsPIC33EP64GS506 PWM interrupt

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Alihan1204
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2019/10/10 01:10:37 (permalink)
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How to work dsPIC33EP64GS506 PWM interrupt

Hello everybody,
 
I have a problem to program my dsPIC33EP64GS506 procesors. I am using MPLAB XC16 debugger console. I am trying to learn interrupts with simple PWM code. But the interrupt doesn't work the way I want. 1000 instruction cycles are required to enter the interrupt, while 200 instruction cycles are required to enter the interrupt. Where do I go wrong?
 
// DSPIC33EP64GS506 Configuration Bit Settings

// 'C' source line config statements

// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Enabled AIVT)

// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)

// FSIGN

// FOSCSEL
#pragma config FNOSC = FRC // Oscillator Source Selection (Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) )
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)

// FOSC
#pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config IOL1WAY = ON // Peripheral pin select configuration bit (Allow only one reconfiguration)
#pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
#pragma config PLLKEN = ON // PLL Lock Enable Bit (Clock switch to PLL source will wait until the PLL lock signal is valid)

// FWDT
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
#pragma config WDTEN = OFF // Watchdog Timer Enable bits (WDT and SWDTEN disabled)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)

// FPOR

// FICD
#pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
#pragma config BTSWP = OFF // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)

// FDEVOPT
#pragma config PWMLOCK = OFF // PWMx Lock Enable bit (Certain PWM registers may only be written after key sequency)
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config DBCC = OFF // DACx Output Cross Connection bit (No Cross Connection between DAC outputs)

// FALTREG
#pragma config CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)

// FBTSEQ
#pragma config BSEQ = 0xFFF // Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active (Enter Hexadecimal value)
#pragma config IBSEQ = 0xFFF // The one's complement of BSEQ; must be calculated by the user and written during device programming. (Enter Hexadecimal value)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>
#include <libpic30.h>

//_FOSCSEL(FNOSC_FRCPLL & IESO_OFF); // Select Internal FRCPLL at POR
//_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_NONE); //Enable Clock Switching and Configure Primary Oscillator disabled
//_FWDT(WDTEN_OFF);

#define FCY 20000000
#define FOSC 40000000
#define FPWM 20000

void Clock_Initialize(void)
{
    //Fcy = 20MHz
    //Fosc = 2 * FCY = 40MHz
    
    //FPLLI= FIN*(1/N1) 0.8MHz<=FPLLI<=8.0 MHz Olmak zorunda
    //FVCO=FIN*(M/N1) 120MHz<=FVCO<=340MHz
    //FPLLO = FIN*(M/(N1*N2)) FPLLO output frequency
    
    PLLFBD = 63; //M = PLLPRE + 2
    CLKDIVbits.PLLPOST = 2; //N2 = 2*(PLLPOST+1)
    CLKDIVbits.PLLPRE = 0; //N1 = PLLDIV + 2
    
    //F_pllo = 40MHz
    //F_vco = 240MHz
    //F_ın = 7.37 MHz
    //F_pllı = 3.685 MHz
    
    // Initiate Clock Switch to FRC oscillator with PLL (NOSC=0b001)
    __builtin_write_OSCCONH(0x01);
    __builtin_write_OSCCONL(OSCCON | 0x01);
    // Wait for Clock switch to occur
    while (OSCCONbits.COSC!= 0b001);
    // Wait for PLL to lock
    while (OSCCONbits.LOCK!= 1);
    
    return;
}

void PWM_Initialize (void)
{
    // PCLKDIV 1;
    PTCON2 = 0x00;
    
    // PTPER 2000;
    PTPER = FOSC/FPWM;
    
    // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time actively applied for all output modes; TRGIEN enabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled;
    PWMCON1 = PWMCON2 = 0x0500;
    
    //FLTDAT PWM1L Low, PWM1H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM1L Low, PWM1H Low; OVRDAT PWM1L Low, PWM1H Low; POLH disabled;
    __builtin_write_PWMSFR(&IOCON1, 0xC000, &PWMKEY);
    //FLTDAT PWM2L Low, PWM2H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM2L Low, PWM2H Low; OVRDAT PWM2L Low, PWM2H Low; POLH disabled;
    __builtin_write_PWMSFR(&IOCON2, 0xC000, &PWMKEY);

    //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM1H, PWM1L pins to FLTDAT values- Latched; IFLTMOD disabled; FLTSRC FLT1;
    __builtin_write_PWMSFR(&FCLCON1, 0x408, &PWMKEY);
    //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM2H, PWM2L pins to FLTDAT values- Latched; IFLTMOD disabled; FLTSRC FLT1;
    __builtin_write_PWMSFR(&FCLCON2, 0x408, &PWMKEY);

    //MDC = 1000
    MDC = PTPER/2;
    
    //PHASE1 = 0;
    PHASE1 = 0x00;
    // PHASE2 0;
    PHASE2 = 0x00;
    
    //DTR1 = 0;
    DTR1 = 0x00;
    // DTR2 0;
    DTR2 = 0x00;
    
    // ALTDTR1 0;
    ALTDTR1 = 0x00;
    // ALTDTR2 0;
    ALTDTR2 = 0x00;
    
    //Interrupts
    IFS5bits.PWM1IF = 0;
    IEC5bits.PWM1IE = 1;
    //
    IFS5bits.PWM2IF = 0;
    IEC5bits.PWM2IE = 1;

    // SYNCOEN disabled; SEIEN disabled; SESTAT disabled; SEVTPS 1; SYNCSRC SYNCI1; SYNCEN disabled; PTSIDL disabled; PTEN enabled; EIPU disabled; SYNCPOL disabled;
    PTCON = 0x8000;
}

int main(void)
{
    INTCON2bits.GIE = 1; // Interrupt is enabled
    Clock_Initialize();
    PWM_Initialize();
    while(1);
}

void __attribute__((__interrupt__, __auto_psv__)) _PWM1Interrupt( )
{
    IFS5bits.PWM1IF = 0; //clear interrupt flag
}

void __attribute__((__interrupt__, __auto_psv__)) _PWM2Interrupt( )
{
    IFS5bits.PWM2IF = 0;
}

 
 
#1

2 Replies Related Threads

    ric
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    Re: How to work dsPIC33EP64GS506 PWM interrupt 2019/10/14 01:09:06 (permalink)
    0
    Alihan1204
    ...
    1000 instruction cycles are required to enter the interrupt, while 200 instruction cycles are required to enter the interrupt.

    Huh?
    Why the two different figures?
    What are you actually trying to say?
    (Was the second figure meant to be how long to EXIT?)
     
    How are you measuring the number of cycles?
    post edited by ric - 2019/10/14 01:15:32

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    #2
    Alihan1204
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    Re: How to work dsPIC33EP64GS506 PWM interrupt 2019/10/16 04:24:21 (permalink)
    0
    Hello ric,
     
    Actually, I'm trying to say. I couldn't run PWM the way I wanted. But I found out that it was because of the wrong PTPER value.
     
    The 1 / Fosc value indicates the number of seconds it takes to pass 1 cycle.In this way, we find out how many cycles are equal to 50us.
     
    //------------------------

    ACLKCONbits.FRCSEL = 1; //Selects the FRC clock for Auxiliary PLL
    ACLKCONbits.SELACLK = 1; //Auxiliary oscillators provide the source clock for the auxiliary clock divider
    ACLKCONbits.APSTSCLR = 0b111; // Auxiliary clock output divider bit divided-by-1
    ACLKCONbits.ENAPLL = 1; //APLL is enabled
     
    //---------------------------
    //PWM Generation
    // PTPER 47192;
    PTPER = ((ACLK*8)/FPWM)-8;
    //Master Duty Cycle = 23596;
    MDC = PTPER/2;


     
     
    #3
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