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Hot!MCLR capacitor (RC) required for PIC24FJ64GA705 ?

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Murton Pike Systems
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 16:07:50 (permalink)
0
I find SMD devices a nightmare.
I tend to use SOIC parts as they are larger footprints.
Even then sometimes despite trying hard I get a dry joint with hand soldering.
I use plenty of flux paste but even then still get the odd dry joint.
I can only guess its due to oxidised pins.
Sometimes just reflowing the joints fixes a dead PIC.
 
#21
cea
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 16:08:00 (permalink)
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So here's the deal, the PIC24FJ64GA705 has some issues with the oscillator. I opened a case with microchip support here and the result was an updated errata.
 
It is far from clear that any of this is relevant to your issues but if you are doing clock switching you really need to check for oscillator start faults.
#22
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 16:18:42 (permalink)
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Not quite, these first boards were programmed in-house by our technician.
 
UPDATE:
The famous board in question was dead again this morning.
Upon connecting the IPC/ICD, and pressing "connect" the board suddenly came alive again.
 
I have received 5 boards back from rework, new CPU fitted.
Those are all working fine.
 
Hmm.
 
#23
NorthGuy
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 16:52:43 (permalink)
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user2x
UPDATE:
The famous board in question was dead again this morning.
Upon connecting the IPC/ICD, and pressing "connect" the board suddenly came alive again.



I would suspect a bad contact somewhere.
#24
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 18:53:51 (permalink)
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charles@socketcom
So here's the deal, the PIC24FJ64GA705 has some issues with the oscillator. I opened a case with microchip support here and the result was an updated errata.
 
It is far from clear that any of this is relevant to your issues but if you are doing clock switching you really need to check for oscillator start faults.


Is that the Errata:
 Oscillator   19.  When FSCM is enabled and selected clock fails, an oscillator trap may not occur
?
 
Regards
X
 
 
#25
cea
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/10 22:55:21 (permalink)
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user2x
Is that the Errata:
Oscillator 19. When FSCM is enabled and selected clock fails, an oscillator trap may not occur?

Yes I think so but, there are several issues in the DS80000718F errata that concern the oscillator module.

See Silicon Errata issues 4,17,19,20 and Data Sheet Clarification item 2.

Depending on some conditions that Microchip either cannot or will not describe in full there are modes that result in oscillator module failure.

All I can do is suggest that you read my description of the condition I can reproduce using the DM240016 / PIC24FJ256GA7 Curiosity Development Board to see if there is any relationship to your implementation. I suspect there may be more ways to cause an oscillator failure. At present I do not know where or how to look for more.

What I have found is that a very similar oscillator module in the PIC24FJ128GA204 does not fail like the PIC24FJ256GA705 does when using the same test application.

It's possible that the PIC24FJ256GA705 has a fundamental flaw that would be expensive to correct and that future sales of the part would be unlikely to recover.

I make this speculation based on the way the errata describes the issues with the oscillator module in such opaque, uninformative language. In my view the language may be vague on purpose or the writer is just incompetent.
post edited by charles@socketcom - 2020/09/10 22:56:24
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user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/13 18:37:50 (permalink)
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Ok, I am still looking at the board (as above) with the problem.
 
 
I think it could definitely be a random oscillator startup problem.
 
Would routing the oscillator out on a port pin indicate this issue?
 
 EDIT: Yes it does.
 
Look at the waveform when NOT ok!!!
 
 
 
 
post edited by user2x - 2020/09/13 19:17:06

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#27
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/13 21:16:08 (permalink)
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Expanding the waveform "Problem1", shows that the oscillator starts for 2 cycles and then stops. It then remains low for ~180us, then goes high until the cycle repeats.
 
post edited by user2x - 2020/09/13 22:14:50

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#28
cea
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 00:15:26 (permalink)
5 (1)
It would appear that errata item 4 could be your issue but it depends on how you have configured the system oscillator. To badly quote Lewis Carroll, "The time has come," the Walrus said, "To talk of many things: Of config words and bypass caps and clock switch code and PLL settings."
 
So if you would describe how you need your PIC to start from power on reset it may show what if any of the issues described in the errata could be involved.
post edited by cea - 2020/09/14 15:34:57
#29
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 14:21:27 (permalink)
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Oh ,man, sorry everyone.
 
I was not able to post here since yesterday. Access denied, you do not habve permissions and the I cannot log in from any mobile device.
 
 
 
Anyway here is the config code:
There is no PLL or anything fancy. sut plain 8MHz from the FRC (or 4MHz)
 

 
 
 
 
 
 
 
// FOSCSEL
#pragma config FNOSC = OSCFDIV //FRC    // Oscillator Source Selection (Internal Fast RC (FRC) through divider)
#pragma config PLLMODE = DISABLED       // PLL Mode Selection (No PLL used; PLLEN bit is not available)
#pragma config IESO = OFF               // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

 
 
 
 
 
 
 

// FOSC
#pragma config POSCMD = NONE            // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
//#pragma config OSCIOFCN = ON            // OSC2 Pin Function bit (OSC2 is GPIO )
#pragma config OSCIOFCN = OFF            // OSC2 Pin Function bit (OSC2)

 
 
 
 
 
 
 
#pragma config SOSCSEL = OFF            // SOSC Power Selection Configuration bits (Digital (SCLKI) mode)
#pragma config PLLSS = PLL_FRC          // PLL Secondary Selection Configuration bit (PLL is fed by the on-chip Fast RC (FRC) oscillator)
#pragma config IOL1WAY = OFF            // Peripheral pin select configuration bit (Allow multiple reconfigurations)
#pragma config FCKSM = CSDCMD           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock 

 
 
 
 
 
 
 
 
/****   And in main, I have this *****/


 
#if (SYSTEM_CLK == OSC_4MHZ)

    OSCDIV = 0x0001;            //div by 2 8/2 = 4MHz
#elif (SYSTEM_CLK == OSC_8MHZ)
    OSCDIV = 0x0000;            //div by 1 8/1 = 8MHz
#else
    #error "****  NO valid SYSTEM_CLK defined"
#endif   

    CLKDIVbits.RCDIV = 0;      //input to divider = FRC fast RC oscillator  





 
The system runs at 8MHz clock speed.
 
 
I have just re-read that #4 errata but cannot fully understand it.
 
Does that apply to my setup at all? 
Yesterday, I concluded that none of those errata apply to my setup but now I am confused again.
 
 
post edited by user2x - 2020/09/14 16:04:17
#30
cea
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 16:05:41 (permalink)
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Your code looks good.
 
Your oscilloscope pictures appear to me to be showing a lockup after oscillator fault. I suspect that the oscillator fault is asserted but your configuration words have disabled clock switching and oscillator fault detection.
 
In my opinion you have discovered an issue that the errata does not seem to cover.
 
Try changing:
#pragma config FCKSM = CSDCMD
to:
#pragma config FCKSM = CSECME

And add an oscillator trap handler:
#define FSYS        (8000000L)
#define FCY         (FSYS/2)    /* Instruction Cycle Frequency */
/*
 * WARNING: Not a portable function.
 *          Maximum 16MHz instruction cycle clock.
 *          Minimum  8Khz instruction cycle clock.
 */
void delay_ms( unsigned long delay )
{
    do
    {
        asm("repeat  %0\n nop\n":: "r" (FCY/1000L-7L));
    } while(delay--);
}
/* 
 * Trap Handler for oscillator fail
 */ 
void __attribute__((interrupt,no_auto_psv)) _OscillatorFail(void)
{
    for(;;)
    {
        /* Flash the RED RGB LED from the oscillator fail trap */
        INTCON1bits.OSCFAIL = 0;
        LATAbits.LATA0  = 1;     /* turn RED LED on */
        delay_ms(1);
        ClrWdt();
        LATAbits.LATA0  = 0;     /* turn RED LED off */
        delay_ms(199);
        ClrWdt();
    }
 }

 
post edited by cea - 2020/09/14 16:16:00
#31
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 16:27:09 (permalink)
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I did add a handler yesterday.
But did not change the config you mentioned.
 
I then re-read errata  19 which is stating something about that Oscillator fail trap not working correctly either.
 

19. Module: Oscillator
If a clock failure event occurs when the Fail-Safe Clock Monitor (FSCM) is enabled,
the oscillator trap may not occur.
Instead of the oscillator trap, a clock failure condition can result in instruction misexecution
with other traps or Resets generated.
 
Work around
None.
 

 
 
post edited by user2x - 2020/09/14 16:32:44
#32
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 17:44:18 (permalink)
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UPDATE:
I have changed the config bits for allowing fail detect and oscillator switch as per your suggestion:

#pragma config FCKSM = CSECME

 
The failure then changes from the previous waveform to this one:
I now see 4 clock cycles and the line stays high instead of low. The whole thing repeats again at ~420Hz.
 
The Oscillator trap handler did not execute as far as I can tell.
 
 

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#33
ric
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 17:51:50 (permalink)
0
Can we see a hi-res photo of the whole board?
Are you sure you have a good bypass capacitor connected as close as possible toi EACH pair of power pins?
 

I also post at: PicForum
Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
NEW USERS: Posting images, links and code - workaround for restrictions.
To get a useful answer, always state which PIC you are using!
#34
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 18:43:50 (permalink)
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No - unfortunately.
But you can rest assured that the whole board is only 25mm x 30mm big and the CPU is right at the bypass caps. it is also a multilayer board with proper ground and power planes.   
post edited by user2x - 2020/09/14 18:59:02
#35
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 18:48:03 (permalink)
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Here is s screenshot of a part of it. I highlighted the decoupling caps and C4 is the VCap.
It is mostly 0402 stuff

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#36
user2x
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 21:22:00 (permalink)
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UPDATE:
It seems to follow the chips.
 
I have had 4 problematic chips replaced on 4 boards.  They came back working.
I then had the same 4 previously removed chips fitted to 4 new boards.
They all came back with the same issue as before.
 
Oh man...
 
 
#37
dan1138
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/14 23:44:46 (permalink)
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user2x
UPDATE:
It seems to follow the chips.
 
I have had 4 problematic chips replaced on 4 boards.  They came back working.
 
I then had the same 4 previously removed chips fitted to 4 new boards.
 
They all came back with the same issue as before.
 
Oh man...

Here's a wild speculation that the fractional divider function may be causing your issues.

As an experiment try to set your clock selection like this:
#pragma config FNOSC = FRCPLL, PLLSS = PLL_FRC
#pragma config POSCMD = NONE, PLLMODE = PLL4X

void main(void)
{
    
    ...
    
    CLKDIV  = 0x0180; /* set FRCPLL as fractional divider input, set CPDIV for divide by 4 */
    
    ...
    
}

I think this will direct an 8MHz oscillator into the CPU to create a 4MHz instruction clock without passing through the fractional divider.

I am just guessing here as I cannot reproduce your fault with the chips I have on hand.
#38
NorthGuy
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/15 06:15:19 (permalink)
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You can set FNOSC = FRC. I think that's what is used during programming, so should work. I tested hundrds of different PICs and I've never seen FRC failing.
 
Have you tried running the bad PICs with the programmer still attached?
#39
cea
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Re: MCLR capacitor (RC) required for PIC24FJ64GA705 ? 2020/09/15 12:48:17 (permalink)
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user2x
UPDATE:
It seems to follow the chips.
 
I have had 4 problematic chips replaced on 4 boards.  They came back working.
I then had the same 4 previously removed chips fitted to 4 new boards.
They all came back with the same issue as before.
 
Oh man...

I realize that you need to keep most of the information about your project private,
so I created this test code for you:
/*
 * File:   main.c
 * Author: cea
 * Target: PIC24FJ256GA702
 * Compiler: XC16 v1.41
 * IDEP MPLABX v5.40
 *
 * Created on September 15, 2020, 11:26 AM
 *
 *                                 PIC24FJ256GA702
 *                  +-------------------:_:-------------------+
 *  SW1 ICD_VPP --> :  1 MCLR                         VDD  28 : <-- 3v3
 *          POT < > :  2 RA0/RP26/AN0                 VSS  27 : <-- GND
 *              < > :  3 RA1/RP27/AN1        AN9/RP15/RB15 26 : < >
 *              < > :  4 RB0/PGD1/AN2        AN6/RP14/RB14 25 : < >
 *              < > :  5 RB1/PGC1/AN3        AN7/RP13/RB13 24 : < > LED_DS4
 *              < > :  6 RB2/RP2/SDA2/AN4    AN8/RP12/RB12 23 : < > LED_DS3
 *              < > :  7 RB3/RP3/SCL2/AN5        RP11/RB11 22 : <*> LED_DS2
 *              - > :  8 VSS                     RP10/RB10 21 : <*> LED_DS1
 *              < > :  9 RA2/OSCI                     VCAP 20 : <-- 10uF
 *     CLOCKOUT < > : 10 RA3/OSCO                     VSS  19 : <-- GND
 *              < > : 11 RB4/RP4             SDA1/RP9/RB9  18 : < >
 *              < > : 12 RA4                 SCL1/RP8/RB8  17 : <*>
 *          3v3 --> : 13 VDD                     RP7 /RB7  16 : <*>
 *      ICD_PGD <*> : 14 RB5/PGD3                PGC3/RB6  15 : <*> ICD_PGC
 *                  +-----------------------------------------+
 *                                    DIP-28
 *               * Indicates 5.5V tolerant input pins.
 *
 * Description:
 *
 *  Test application to look for clock start issue.
 *
 *      See: https://www.microchip.com/forums/FindPost/1114791
 *
 * This is what the PICkit3 thinks about my PIC24FJ256GA702:
 *      
 *      *****************************************************
 *
 *      Connecting to MPLAB PICkit 3...
 *
 *      Currently loaded firmware on PICkit 3
 *      Firmware Suite Version.....01.56.07
 *      Firmware type..............dsPIC33F/24F/24H
 *
 *      Target voltage detected
 *      Target device PIC24FJ256GA702 found.
 *      Device Revision ID = 3
 *      DEVSN0 = 00000000
 *      DEVSN1 = 00000000
 *
 *      Device Erased...
 *
 *      Programming...
 *
 *      The following memory area(s) will be programmed:
 *      program memory: start address = 0x0, end address = 0x3ff
 *      Programming/Verify complete
 *     
 */
#pragma config FNOSC = FRC, POSCMD = NONE, PLLSS = PLL_FRC, PLLMODE = PLL4X
#pragma config BWRP = OFF, BSS = DISABLED, BSEN = OFF, GWRP = OFF
#pragma config GSS = DISABLED, CWRP = OFF, CSS = DISABLED, AIVTDIS = OFF
#pragma config BSLIM = 0x1FFF, IESO = OFF
#pragma config OSCIOFCN = OFF, SOSCSEL = ON
#pragma config IOL1WAY = OFF, FCKSM = CSECME
#pragma config WDTPS = PS2048, FWPSA = PR128, FWDTEN = OFF, WINDIS = OFF
#pragma config WDTWIN = WIN25, WDTCMX = LPRC, WDTCLK = LPRC, BOREN = OFF
#pragma config LPCFG = OFF, DNVPEN = ENABLE, ICS = PGD3, JTAGEN = OFF
#pragma config ALTCMPI = DISABLE, TMPRPIN = OFF, SOSCHP = OFF, ALTI2C1 = ALTI2CEN
#include "xc.h"
#define FSYS        (8000000L)
#define FCY         (FSYS/2)    /* Instruction Cycle Frequency */
#define LED_ON      (1)
#define LED_OFF     (0)
#define DS1(state)  LATBbits.LATB10=state
#define DS2(state)  LATBbits.LATB11=state
#define DS3(state)  LATBbits.LATB12=state
#define DS4(state)  LATBbits.LATB13=state
/*
 * WARNING: Not a portable function.
 *          Maximum 16MHz instruction cycle clock.
 *          Minimum  8Khz instruction cycle clock.
 */
void delay_ms( unsigned long delay )
{
    do
    {
        asm("repeat  %0\n nop\n":: "r" (FCY/1000L-7L));
    } while(delay--);
}
/* 
 * Trap Handler for oscillator fail
 */ 
void __attribute__((interrupt,no_auto_psv)) _OscillatorFail(void)
{
    for(;;)
    {
        /* Flash the RED RGB LED from the oscillator fail trap */
        INTCON1bits.OSCFAIL = 0;
        LATBbits.LATB12  = 1;     /* turn LED DS3 on */
        delay_ms(1);
        ClrWdt();
        LATBbits.LATB12  = 0;     /* turn LED DS3 off */
        delay_ms(199);
        ClrWdt();
    }
 }
int main(void)
{
    /*
     * Disable all interrupt sources
     */
    __builtin_disi(0x3FFF); /* disable interrupts for 16383 cycles */
    IEC0 = 0;
    IEC1 = 0;
    IEC2 = 0;
    IEC3 = 0;
    IEC4 = 0;
    IEC5 = 0;
    IEC6 = 0;
    IEC7 = 0;
    __builtin_disi(0x0000); /* enable interrupts */
    ANSA   =  0x0001; /* AN0 enabled all others set for digital I/O */
    ANSB   =  0x0000; /* Set for digital I/O */
   
    _NSTDIS = 1;    /* disable interrupt nesting */
       
    LATA = 0;
    LATB = 0;
    TRISA   = 0xFFFF;
    TRISB   = 0xC3FF; /* Make RB10, RB11, RB12, RB13 outputs */
    CLKDIV  = 0x0000; /* set for FRC clock 8MHZ operations */
    for(;;)
    {
        DS4(LED_OFF);
        delay_ms(500);
        DS4(LED_ON);
        delay_ms(500);
    }
}

Please make changes to this code so that the clock fails in your proprietary hardware.
 
If you can get it to fail please post the code as you changed it.
post edited by cea - 2020/09/15 13:47:16
#40
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