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Hot!dsPIC33CK256MP506 High resolution PWM frequency tolerance

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d.giddy
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2019/10/03 16:13:17 (permalink)
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dsPIC33CK256MP506 High resolution PWM frequency tolerance

Hi,
 
I'm using a dsPIC33CK256MP506 in an application that needs highly accurate frequency control (1ppm) and fine phase and duty cycle control. In the data sheet, for high resolution mode, it specifies that the master clock needs to run at 500MHz. The timing specs note only that the maximum master clock frequency is 500MHz. My application needs to use an external clock source to achieve the accuracy required, but also needs to be adjustable between 10-15 MHz. Through appropriate use of the APLL dividers, I can generate a master clock that is within 5% of 500 MHz. My question is whether this is within the tolerance specification for high resolution mode?
 
I also note that one of the status registers contains a high resolution error bit (HRERR) which the detailed data sheet on PWM suggests will be triggered on a clock error. There is no indication of what sort of clock error it reacts to. Is this related to the master clock being within a certain tolerance?
 
Thanks for any assistance.
 
Regards,
 
David.
 
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    du00000001
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/04 12:35:32 (permalink)
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    1 ppm? Wht kind of external oscillator with this precision do you sport?
    And what's its clock jitter specification ?
     
    Anyway: when considering HR PWM, you should add DS70005320C (referred-to within the datasheet) to your reading stuff.
    IIRC, HWPWM employs some special 8-fold PLL circuit plus some "special tricks" to achieve the HR. I expect this PLL to internally achieve 4 GHz (equivalent 250 ps resolution) - 8 times 500 MHz. (Thus the 500 MHz specification.)

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #2
    Nikolay_Po
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/04 13:04:04 (permalink)
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    The dsPIC is not a true signal processing and analog circuit. Generic microcontroller PLL is not good for precision time domain signal processing. Sure you will find considerable amount of a jitter using controller PLL as a clock source for your time-related signals. You may find up to a fraction of a percent of a period jitter. Not a single part per million but much, much more.
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    spdmtl
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/04 15:03:58 (permalink)
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    5% tolerance of 500 MHz is fine, 10% is max MCHP recommended limit.
    The HR/edge placement circuit was designed at a 500 MHz target for CK devices.
     
    The HRERR bit will only set on HR failure itself, not an input clock error.
     
    PLL jitter is relatively low, but not 1ppm by the time it gets to PWM as stated above.
     
    post edited by spdmtl - 2019/10/04 15:08:00
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    d.giddy
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/04 16:33:34 (permalink)
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    Thanks all for the replies. To clarify a bit, I should have said that the frequency resolution and short term accuracy I need is 1 ppm, the jitter requirement is much more relaxed (700 ps or better). I am using the Si514 programmable oscillator which has 0.026 ppb frequency resolution and 25ppm temperature accuracy. With calibration and temperature compensation, I should be able to get close to 1 ppm short term accuracy. It's jitter specification is 11 ps pk-pk and I know that passing it through the dsPIC will degrade this substantially, but this will be OK I think. 
    Sounds like I should be able to make this work, so will try it out.
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    Nikolay_Po
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/05 04:30:06 (permalink)
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    If you're planning a mass production it worth to submit a "case" to Microchip tech. support and ask them about clock frequency variation possibility while using HRPWM. Not fast but you will get an answer of related Microchip engineer.
    Normal operation of several chips at unknown limits can't warrant the absence of problems in mass production. So before you will plan the last, you must be consulted by Microchip about possible frequency limits and PLL operation with external frequency tuning.
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    d.giddy
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    Re: dsPIC33CK256MP506 High resolution PWM frequency tolerance 2019/10/06 15:25:03 (permalink)
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    Thank Nikolay, good suggestion. I'll follow up with them and share any response I get.
    #7
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