dsPIC33CK256MP506 High resolution PWM frequency tolerance
I'm using a dsPIC33CK256MP506 in an application that needs highly accurate frequency control (1ppm) and fine phase and duty cycle control. In the data sheet, for high resolution mode, it specifies that the master clock needs to run at 500MHz. The timing specs note only that the maximum master clock frequency is 500MHz. My application needs to use an external clock source to achieve the accuracy required, but also needs to be adjustable between 10-15 MHz. Through appropriate use of the APLL dividers, I can generate a master clock that is within 5% of 500 MHz. My question is whether this is within the tolerance specification for high resolution mode?
I also note that one of the status registers contains a high resolution error bit (HRERR) which the detailed data sheet on PWM suggests will be triggered on a clock error. There is no indication of what sort of clock error it reacts to. Is this related to the master clock being within a certain tolerance?
Thanks for any assistance.