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Hot!CAN transceiver

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antesther
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2019/09/25 10:00:17 (permalink)
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CAN transceiver

Hello everyone i have a question regarding high-speed and low-speed CAN transceivers,
 
I got a high-speed CAN transceiver (technically designed to run at 1Mbps) running at 100 kbps, i see a strange behavior in my CAN bus, when i disconnect one node the whole nodes stop talking, i already checked configuration and it is fine, do you think that i might be because of the speed the High-speed transceiver is running at? are they capable of handling low speeds??
 
pink: pink 
#1

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    purdyd
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    Re: CAN transceiver 2019/09/26 05:55:18 (permalink)
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    Yes some transceivers will have a minimum rate. Example the tja1050 lists 60kbps. https://www.nxp.com/docs/...ation-note/AN00020.pdf

    If that were the problem you would think adding the node would be the problem, not removing it.

    How is the bus terminated? How long is the wiring? How is it wired? Have you put an oscilloscope on the bus? How many nodes?
    #2
    antesther
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    Re: CAN transceiver 2019/09/26 06:18:16 (permalink)
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    The transceiver i am m using is MCP2561, it doesn't specify the lowest minimum rate.
     
    I got 6 nodes (PIC18F2580), running at 284 Kbps (I increased the one i originally mentioned),120 ohms terminates bus, the length is less than 1 meter, i have the bus running one breadboard, not using twisted pair cable, but since the length is less than 1 meter, then i think it doesn't matter.
     
    The issue i have is that when i disconnect only 1 specific node, all the nodes stop talking and continue talking once i connect the node i disconnected.
     
    Plus, there are some nodes that dont seem to apply filters on certain messages
     
     
    #3
    antesther
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    Re: CAN transceiver 2019/09/26 06:28:35 (permalink)
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    Below you can have an idea of what the bus connections look like
     
    NODE2 receives messages from NODE4
    NODE4 receives messages from NODE2
     
    NODE5 receives messages from NODE6
    NODE6 receives messages from NODE5
     
    NODE1 receives messages from NODE5
     
    NODE3 receives all messages (has its masks set to 0) since sends CAN bus inof via serial to another micro.
     
    In spite of having that configuration, NODE1 accepts messages from NODE2 and NODE6 accepts messages from NODE4 , as if they were ignoring the masks and filters i configured, i swear i already checked the configuration and everything is configured to work as i originally designed it for.
     
     
     
    post edited by antesther - 2019/09/26 06:29:37
    #4
    crosland
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    Re: CAN transceiver 2019/09/26 06:49:47 (permalink)
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    There are lots of timings that you need to setup in the PIC CAN controller. If you change the bus speed you need to revisit all the other timings and adjust them appropriately.
     
    See the data sheet and the various Microchip CAN app notes.
    #5
    purdyd
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    Re: CAN transceiver 2019/10/04 14:37:37 (permalink)
    5 (1)
    antesther
    The transceiver i am m using is MCP2561, it doesn't specify the lowest minimum rate.
     
    I got 6 nodes (PIC18F2580), running at 284 Kbps (I increased the one i originally mentioned),120 ohms terminates bus, the length is less than 1 meter, i have the bus running one breadboard, not using twisted pair cable, but since the length is less than 1 meter, then i think it doesn't matter.
     
    The issue i have is that when i disconnect only 1 specific node, all the nodes stop talking and continue talking once i connect the node i disconnected.
     
    Plus, there are some nodes that dont seem to apply filters on certain messages
     
     


     
    CAN bus requires two (2) 120 ohm terminations.  Preferably at alternate ends of the network.  At low baud rates you can get away with one.  
     
    As baud rate goes up, cabling matters more and more as do the settings of the CAN controller.  Sampling point, sjf, etc.
     
    the MCP2561 has a stdby pin, make sure you are driving it low.
     
    Have you looked at your bus with an oscilloscope?
     
    How do you know it is working?



    #6
    antesther
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    Re: CAN transceiver 2019/10/06 15:59:30 (permalink)
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    Hello, my CAN bus is terminated with one pair of 120 ohm resistors.
     
    I know it´s working because i defined a sequence where leds turn on and off when messages are received.
     
    The particular Node im having trouble with is the one quoted below,
     
    as you may noticed, i got 3 filters for message reception, however, it is accpeting messages from 3 nodes, when it souldnt even acceptem.
     
     
     

    /* File: main.c
    * Author: anton
    * This code belongs to and only to NODE2 (Temperature Sensor)
    * This NODE will accept messages from NODE2 (TEMP SENSOR) and Send RPM values to FAN(Node 3)
    * Created on May 30, 2019, 11:21 PM
    */
    // CONFIG1H
    #pragma config OSC = IRCIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
    #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
    // CONFIG2L
    #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
    #pragma config BOREN = BOHW // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
    #pragma config BORV = 3 // Brown-out Reset Voltage bits (VBOR set to 2.1V)
    // CONFIG2H
    #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
    #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
    // CONFIG3H
    #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
    #pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
    #pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
    // CONFIG4L
    #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
    #pragma config BBSIZ = 1024 // Boot Block Size Select bit (1K words (2K bytes) boot block)
    #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
    // CONFIG5L
    #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
    #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
    #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
    #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)
    // CONFIG5H
    #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
    #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
    // CONFIG6L
    #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
    #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
    #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
    #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
    // CONFIG6H
    #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
    #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
    #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
    // CONFIG7L
    #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
    // CONFIG7H
    #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
    // #pragma config statements should precede project file includes.
    // Use project enums instead of #define for ON and OFF.
    #include <xc.h>
    #include <math.h>
     

    #define _XTAL_FREQ 4000000
    //#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000.0)))
    short int contador = 0;
    char switcher;
    //unsigned FULL_DATA_BYTE[16];
    float last_value;
    float current_value;
    float data_byte1;
    float data_byte2;
    int g;
    float *w;
    signed int SUM;
    int b = 0;
    int c = 1;
    unsigned int ON_DATA_BYTE_1 = 0b11111111;
    unsigned int ON_DATA_BYTE_2 = 0b11111111;
    unsigned int OFF_DATA_BYTE_1 = 0b10101010;
    unsigned int OFF_DATA_BYTE_2 = 0b10101010;

    float final_decimal_value = 0;
    //unsigned int *EESTRUCT_RXB0_D0[8];
    //unsigned int *EESTRUCT_RXB0_D1[8];
    //unsigned int *EESTRUCT_RXB1_D0[8];
    //unsigned int *EESTRUCT_RXB1_D1[8];
    //unsigned int *EESTRUCT_B0_D0[8];
    //unsigned int *EESTRUCT_B0_D1[8];

    //this variable is equal to DATA_BYTE_1 + DATA_BYTE_2

    int d;
    float Binary_Base_Number = 2.0;
    float exponente;
     
    void Buffers_Registers_AND_MCU_SetUp(void);
    void Received_Messages_Processing(void);
    //void CAN_BIT_FRAME_Transmit(unsigned char *r, unsigned char *s);
    void CAN_BIT_FRAME_Transmit(unsigned int *data_byte_1,unsigned int *data_byte_2); //ONLY 4 TESTING
    //void ESTRUCTs_assignments(void);
     

    void main(void) //**MAIN**
    { TRISAbits.TRISA0 = 0;
    TRISAbits.TRISA1 = 0;
    LATAbits.LATA0 = 0;
    LATAbits.LATA1 = 0;
    TRISBbits.TRISB2 = 0; //PIN RA0 WILL BE AN OUTPUT 0=OUTPUT, 1=INPUT (TX)
    TRISBbits.TRISB3 = 1; //PIN RA0 WILL BE AN OUTPUT 0=OUTPUT, 1=INPUT (RX)
    CANCONbits.REQOP0 = 0; //REQUEST CONFIGURATION MODE
    CANCONbits.REQOP1 = 0; //REQUEST CONFIGURATION MODE
    CANCONbits.REQOP2 = 1; //REQUEST CONFIGURATION MODE
    while (CANCONbits.REQOP0 != 0 && CANCONbits.REQOP1 != 0 && CANCONbits.REQOP2 != 1)
    {

    }
    ECANCONbits.MDSEL0 = 1; //LEGACY MODE
    ECANCONbits.MDSEL1 = 0;
    BRGCON1bits.SJW0 = 1;
    BRGCON1bits.SJW1 = 0; //284 kbps
    BRGCON1bits.BRP0 = 0;
    BRGCON1bits.BRP1 = 0;
    BRGCON1bits.BRP2 = 0;
    BRGCON1bits.BRP3 = 1;
    BRGCON1bits.BRP4 = 0;
    BRGCON1bits.BRP5 = 0;
    //
    //BRGCON2 = 0xBC; //SAMPLING BIT = ONCE PER SECOND, SEG2PTHS = FREELY PROGRAMMABLE
    BRGCON2bits.SAM = 0;
    BRGCON2bits.PRSEG0 = 1;
    BRGCON2bits.PRSEG1 = 0;
    BRGCON2bits.PRSEG2 = 0;
    BRGCON2bits.SEG1PH0 = 1;
    BRGCON2bits.SEG1PH1 = 0;
    BRGCON2bits.SEG1PH2 = 0;
    BRGCON2bits.SEG2PHTS = 1; //FREELY PROGRAMMABKE
    BRGCON3bits.SEG2PH0 = 1;
    BRGCON3bits.SEG2PH1 = 1;
    BRGCON3bits.SEG2PH2 = 0;
    OSCCONbits.IDLEN = 0;
    OSCCONbits.IRCF0 = 0;
    OSCCONbits.IRCF1 = 1;
    OSCCONbits.IRCF2 = 1;
    OSCCONbits.SCS0 = 0;
    OSCCONbits.SCS1 = 1;
    //
    //OSCTUNE = 0x20; //INSTRC = DISABLED, PLLEN = 1 (PLL X4 ENABLED) BIT5 = 0 (DEFAULT), TUN = 00000 (OSCILLATOR MODULE RUNNING AT CALIBRATED FREQUENCY)
    OSCTUNEbits.PLLEN = 1;
    OSCTUNEbits.TUN0 = 0;
    OSCTUNEbits.TUN1 = 0;
    OSCTUNEbits.TUN2 = 0;
    OSCTUNEbits.TUN3 = 0;
    OSCTUNEbits.TUN4 = 0;
    //CONFIG1H = 0x28; //IESO = OFF, FCMEN = ON, FOSC = 1000 (internal osc block ra6 and ra7)
    // TRISB = 0x08; //SET RB2 AS CANTX AND RB3 AD CANRX AS INPUT AND OUTPUT



    //PIN RA0 WILL BE AN OUTPUT 0=OUTPUT, 1=INPUT
    //LATAbits.LATA0 = 1; //DRIVE PIN RA0 TO HIGH (UPON POWERING UP MCU, MOTOR WILL BE ON)
    //RECEIVE BUFFERS CONFIGURATION START MARK *************
    //RXB0 CONFIG INIT
    //PIE3bits.RXB0IE = 0; //enable this receive buffer interrupt
    RXFCON0bits.RXF0EN = 1;
    MSEL0bits.FIL0_0 = 0; //Select Acceptance Mask 0 = RXM0SIDL<->RXMOSIDH
    MSEL0bits.FIL0_1 = 0;
    // RXF0SIDH = 0x3E; //0011 1110 1F5 (NODE1 ID HYGH BYTE)
    RXF0SIDLbits.RXF0SID0 = 1;
    RXF0SIDLbits.RXF0SID1 = 1;
    RXF0SIDLbits.RXF0SID2 = 1;
    RXF0SIDHbits.RXF0SID3 = 0;

    RXF0SIDHbits.RXF0SID4 = 1;
    RXF0SIDHbits.RXF0SID5 = 1;
    RXF0SIDHbits.RXF0SID6 = 1;
    RXF0SIDHbits.RXF0SID7 = 1;
    RXF0SIDHbits.RXF0SID8 = 1;
    RXF0SIDHbits.RXF0SID9 = 0;
    RXF0SIDHbits.RXF0SID10 = 0;

    // RXF0SIDL = 0x5; //0101 1F5 (NODE3 ID LOW BYTE)

    //RXM0SIDH = 0x1;
    RXM0SIDHbits.RXM0SID3 = 1;
    RXM0SIDHbits.RXM0SID4 = 0;
    RXM0SIDHbits.RXM0SID5 = 0;
    RXM0SIDHbits.RXM0SID6 = 0;
    RXM0SIDHbits.RXM0SID7 = 0;
    RXM0SIDHbits.RXM0SID8 = 0;
    RXM0SIDHbits.RXM0SID9 = 0;
    RXM0SIDHbits.RXM0SID10 = 0;


    //RXM0SIDL = 0x7;
    RXM0SIDLbits.RXM0SID0 = 1;
    RXM0SIDLbits.RXM0SID1 = 1;
    RXM0SIDLbits.RXM0SID2 = 1;

    RXB0CONbits.RXB0M1 = 0; //receive only valid messages with standard id
    RXF0SIDLbits.EXIDEN = 0; //filter will only accept ONLY standard ID messages
    // //RXB0 CONFIG END
    // //...
    // //RXB1 CONFIG INIT
    // //PIE3bits.RXB1IE = 1;
    RXFCON0bits.RXF2EN = 1;
    MSEL0bits.FIL2_0 = 0; //Select Acceptance Mask 0 = RXM0SIDL<->RXMOSIDH
    MSEL0bits.FIL2_1 = 0;
    //RXF1SIDH = 0x3E; //0011 1110 1F5 (NODE2 ID HYGH BYTE)
    RXF2SIDLbits.RXF2SID0 = 1;
    RXF2SIDLbits.RXF2SID1 = 1;
    RXF2SIDLbits.RXF2SID2 = 1;
    RXF2SIDHbits.RXF2SID3 = 0;

    RXF2SIDHbits.RXF2SID4 = 1;
    RXF2SIDHbits.RXF2SID5 = 1;
    RXF2SIDHbits.RXF2SID6 = 1;
    RXF2SIDHbits.RXF2SID7 = 1;
    RXF2SIDHbits.RXF2SID8 = 1;
    RXF2SIDHbits.RXF2SID9 = 0;
    RXF2SIDHbits.RXF2SID10 = 0;
    //RXF1SIDL = 0x5; //0101 1F5 (NODE2 ID LOW BYTE)

    //RXM1SIDH = 0x1;
    RXM1SIDHbits.RXM1SID3 = 1;
    RXM1SIDHbits.RXM1SID4 = 0;
    RXM1SIDHbits.RXM1SID5 = 0;
    RXM1SIDHbits.RXM1SID6 = 0;
    RXM1SIDHbits.RXM1SID7 = 0;
    RXM1SIDHbits.RXM1SID8 = 0;
    RXM1SIDHbits.RXM1SID9 = 0;
    RXM1SIDHbits.RXM1SID10 = 0;
    //RXM1SIDL = 0x7;
    RXM1SIDLbits.RXM1SID0 = 1;
    RXM1SIDLbits.RXM1SID1 = 1;
    RXM1SIDLbits.RXM1SID2 = 1;
    // //
    RXB1CONbits.RXB1M1 = 0; //receive only valid messages with standard id
    RXF2SIDLbits.EXIDEN = 0; //filter will only accept ONLY standard ID messages
    //RXB1 CONFIG END
    // //...
    // B0 BUFFER CONFIG INIT
    //BIE0.B0IE = 1; //enable receive buffer b0 interrupt
    RXFCON0bits.RXF7EN = 1; //RXF7 IS ENABLED (RECEIVER FILTER)
    //RXFBCON3 = 0x2; //0010 FILTER 7 IS ASSOCIATED WITH B0
    RXFBCON3bits.F7BP_0 = 0;
    RXFBCON3bits.F7BP_1 = 1; //FILTER 7 IS ASSOCIATED WITH B0
    RXFBCON3bits.F7BP_2 = 0;
    RXFBCON3bits.F7BP_3 = 0;
    // //
    BSEL0bits.B0TXEN = 0; //buffer is configured in Receive Mode ((CHECK LIBRARY DECLARATION))
    MSEL1bits.FIL7_0 = 0; //USE RXM0 AS MASK FOR THIS FILTER
    MSEL1bits.FIL7_1 = 0; //USE RXM0 AS MASK FOR THIS FILTER
    B0CONbits.RXM1 = 0; //Accept messages as per Filters and Masks
    //RXF7SIDH = 0x3E; //0011 1110 1F4 (NODE2 ID HYGH BYTE)
    RXF7SIDLbits.RXF7SID0 = 1;
    RXF7SIDLbits.RXF7SID1 = 1;
    RXF7SIDLbits.RXF7SID2 = 1;
    RXF7SIDHbits.RXF7SID3 = 0;

    RXF7SIDHbits.RXF7SID4 = 1;
    RXF7SIDHbits.RXF7SID6 = 1;
    RXF7SIDHbits.RXF7SID5 = 1;
    RXF7SIDHbits.RXF7SID6 = 1;
    RXF7SIDHbits.RXF7SID7 = 1;
    RXF7SIDHbits.RXF7SID8 = 1;
    RXF7SIDHbits.RXF7SID9 = 0;
    RXF7SIDHbits.RXF7SID10 = 0;
    //RXF7SIDL = 0x5; //0101 1F4 (NODE2 ID LOW BYTE)


    //BO BUFFER CONFIG END
    //RECEIVE BUFFERS CONFIGURATION END MARK***********
    //REQUEST CONFIG MODE
    //OSCCON = 0x6A; //IDLEN = 0, IRCF = 110 (4 MHZ) OSTS = 1 (WAIT 1024 CYCLES FOR STABLE OSCILLATIONS) IOFS = 0 (INITIALIZE OSCILLATOR STATUS IN NOT STABLE MODE), SCS = 10 (EMPLOYING INTERNAL OSCILLATOR BLOCK)
    CANCONbits.REQOP0 = 0; //REQUEST NORMAL MODE
    CANCONbits.REQOP1 = 0; //REQUEST NORMAL MODE
    CANCONbits.REQOP2 = 0; //REQUEST NORMAL MODE

    while (CANSTATbits.OPMODE0 == 0 && CANSTATbits.OPMODE1 == 0 && CANSTATbits.OPMODE2 == 1)
    {

    }

    while(1)
    {

    if (RXB0CONbits.RXB0FUL || RXB1CONbits.RXB1FUL || B0CONbits.B0RXFUL)
    {
    Received_Messages_Processing();
    }

    if (!LATAbits.LA1)
    {
    CAN_BIT_FRAME_Transmit(&ON_DATA_BYTE_1,&ON_DATA_BYTE_2);
    }
    else
    {
    CAN_BIT_FRAME_Transmit(&OFF_DATA_BYTE_1,&OFF_DATA_BYTE_2);
    }

    if (LATAbits.LA0)
    {
    CAN_BIT_FRAME_Transmit(&OFF_DATA_BYTE_1,&OFF_DATA_BYTE_2);
    }
    else
    {
    CAN_BIT_FRAME_Transmit(&ON_DATA_BYTE_1,&ON_DATA_BYTE_2);
    }
    __delay_ms(200);
    }
    }
    void Received_Messages_Processing(void)
    {
    if (RXB0CONbits.RXB0FUL)
    {
    if (RXB0D0 == 0b11111111 && RXB0D1 == 0b11111111)
    {
    LATAbits.LA0 = 1;
    LATAbits.LA1 = 0;
    RXB0CONbits.RXB0FUL = 0;
    }
    else if (RXB0D0 == 0b10101010 && RXB0D1 == 0b10101010)
    {
    LATAbits.LA1 = 1;
    LATAbits.LA0 = 0;
    RXB0CONbits.RXB0FUL = 0;
    }

    }

    else if (RXB1CONbits.RXB1FUL)
    {
    if (RXB1D0 == 0b11111111 && RXB1D1 == 0b11111111)
    {
    LATAbits.LA0 = 1;
    LATAbits.LA1 = 0;
    RXB1CONbits.RXB1FUL = 0;
    }
    else if (RXB1D0 == 0b10101010 && RXB1D1 == 0b10101010)
    {
    LATAbits.LA1 = 1;
    LATAbits.LA0 = 0;
    RXB1CONbits.RXB1FUL = 0;
    }

    }
    else if (B0CONbits.B0RXFUL)
    {
    if (B1D0 == 0b11111111 && B1D1 == 0b11111111)
    {
    LATAbits.LA0 = 1;
    LATAbits.LA1 = 0;
    B0CONbits.B0RXFUL = 0;
    }

    else if (B1D0 == 0b10101010 && B1D1 == 0b10101010)
    {
    LATAbits.LA1 = 1;
    LATAbits.LA0 = 0;
    B0CONbits.B0RXFUL = 0;
    }

    }

    return;
    }

    void CAN_BIT_FRAME_Transmit(unsigned int *data_byte_1,unsigned int *data_byte_2)
    {
    if (!TXB0REQ)
    {
    TXB0SIDLbits.EXIDE = 0;
    TXB0DLCbits.DLC0 = 0;
    TXB0DLCbits.DLC1 = 1;
    TXB0DLCbits.DLC2 = 0;
    TXB0DLCbits.DLC3 = 0;
    TXB0SIDLbits.TXB0SID0 = 0; //MESSAGE IDENTIFIER LOW BYTE
    TXB0SIDLbits.TXB0SID1 = 1;
    TXB0SIDLbits.TXB0SID2 = 1;
    TXB0SIDHbits.TXB0SID3 = 0;

    TXB0SIDHbits.TXB0SID4 = 1;
    TXB0SIDHbits.TXB0SID5 = 1;
    TXB0SIDHbits.TXB0SID6 = 1;
    TXB0SIDHbits.TXB0SID7 = 1;
    TXB0SIDHbits.TXB0SID8 = 1;
    TXB0SIDHbits.TXB0SID9 = 0;
    TXB0SIDHbits.TXB0SID10 = 0;
    // TXB0SIDL = 0x4;

    TXB0D0 = *data_byte_1;
    TXB0D1 = *data_byte_2;
    TXB0REQ = 1; //SEND MESSAGE TO CAN BUS! (AS LONG AS BUS IS AVAILABLE)
    while (TXB0REQ != 0) //WAIT FOR MESSAGE TO BE SUCCESSFULLY SENT AND ACKNOWLEDGED BY OTHER NODES 0 = BUFFER IS EMPTY, 1 = BUFFER IS BUSY
    {

    }
    }
    return;
    }
     
     
     
     
    post edited by antesther - 2019/10/06 16:00:35
    #7
    antesther
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    Re: CAN transceiver 2019/10/06 18:34:27 (permalink)
    4 (1)
    I finally solved it! for those out there struggling with this, make sure you dont violate the rules of the 5 recessive or dominant bits, i had mistakenly declared my message ids with six consecutive dominant bits, this goes against NRZ encoding rules of bit stuffing, that made my bus behave quite strangely.
     
    Peace!
    #8
    Jerry Messina
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    Re: CAN transceiver 2019/10/08 03:06:58 (permalink)
    4 (1)
    So you're saying that there's a problem with the CAN controller in the device you're using where it doesn't perform bit-stuffing properly?
     
     
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    antesther
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    Re: CAN transceiver 2019/11/21 16:33:40 (permalink)
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    Hello,
    I am sorry for the delayed answer,
     
    It might be the case, maybe the logic it follows is to add a opposite polarity bit when five consecutive bits of the same polarity are detected, i had placed 6 bits of the same polarity, maybe the can controller ignored it, but it did affect my CAN bus, there were some nodes accepting messages regardless of their filters.
    #10
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