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xfiles_2007
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2019/09/23 20:19:44 (permalink)
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External clock sync

Hi
 
I have a PIC18F26K22. The code I have seems to run at the desired rate. Its using an external clock as its input source.
I think I have a timing issue somewhere along the way (sending data). It results in some data being sent too quickly at times or too slow. (This happens after a minute or so)
 
Is there a way to ensure the input clock is synced to the internal clocks ?
 
Currently my config is this :
 
// CONFIG1H
#pragma config FOSC = ECMP // Oscillator Selection bits (Internal oscillator block)
#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
//#pragma config WDTPS = OFF // Watchdog Timer Postscale Select bits (1:32768)
 
#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

#define _XTAL_FREQ 4500000UL
 
 
I read somewhere I can set certain bits but not sure ?  (T1SYNC )
Is there a way to check wait for a clock edge then perform an action ? (INTEDG) Timer0 ?
 
Im looking at - but its beyond me at the moment. 
http://ww1.microchip.com/downloads/en/DeviceDoc/31011a.pdf
 
 
 
#1

49 Replies Related Threads

    jtemples
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    Re: External clock sync 2019/09/23 22:18:59 (permalink)
    +2 (2)
    Is there a way to ensure the input clock is synced to the internal clocks ?

     
    If you only have one clock source, what else would the clocks be synced to?
     
    T1SYNC

     
    That's if your feeding an external clock into TMR1, which it doesn't sound like you're doing.
     
    Is there a way to check wait for a clock edge then perform an action

     
    A clock edge? Is this a different clock that what you're clocking the PIC with?  Or did you just mean an "edge" from some other source?
    #2
    xfiles_2007
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    Re: External clock sync 2019/09/23 22:44:46 (permalink)
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    jtemples
    If you only have one clock source, what else would the clocks be synced to?
     
     
    Hmm no other clock source just the one.
     
    jtemples
    That's if your feeding an external clock into TMR1, which it doesn't sound like you're doing.
     

    I see. 
     
    jtemples
    A clock edge? Is this a different clock that what you're clocking the PIC with?  Or did you just mean an "edge" from some other source?



    No other clock. So the chip should be executing at the right edges then ? 
     
     
     
     
    #3
    NKurzman
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    Re: External clock sync 2019/09/23 23:16:37 (permalink)
    +1 (1)
    No other clock. So the chip should be executing at the right edges then???
    The input clock is divide by 4. Things happen on the edges the chip designer choose.

    What do you think Sharing a clock will sync?
    #4
    xfiles_2007
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    Re: External clock sync 2019/09/23 23:25:43 (permalink)
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    Yea it seems to be executing ok for a while then something changes after a few mins or so - leading to data being sent a bit slower.
     
     
     
    #5
    ric
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    Re: External clock sync 2019/09/23 23:38:21 (permalink)
    +1 (1)
    Sounds more like a bug in your code. I think you're chasing the wrong horse.
     

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    #6
    xfiles_2007
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    Re: External clock sync 2019/09/24 01:53:38 (permalink)
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    yea going to keep digging in
    #7
    pcbbc
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    Re: External clock sync 2019/09/24 07:59:39 (permalink)
    +1 (1)
    Sending - Sending where? UART? SPI/I2C?
    Too quickly / Too slow - By how much? How are you measuring this?
     
    Otherwise you're on your own, sorry.
    #8
    davea
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    Re: External clock sync 2019/09/24 21:27:11 (permalink)
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    using just 1 clk source
    with PLL off there can't be any dither (the pic will be a perfect divider ) 
    is it true crystal OSC with its own VDD and GND and a low PPM
    or some so so ceramic resonator
     
     
    #9
    xfiles_2007
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    Re: External clock sync 2019/09/24 21:28:21 (permalink)
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    Sending to another device and some bytes after a minute I see the bytes going too quick (doesn't seem to be following the delays I use )which results in errors (checking via logic analyser)
     
    might be turning the tx on and off too many times - after each byte instead of turning it on once, sending all the bytes then turning it off.
     
    #10
    davea
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    Re: External clock sync 2019/09/24 21:41:56 (permalink)
    +1 (1)
    might be turning the tx on and off too many times
    that's a bad thing...
    leave it on all the time
    check the UART bits to tell when it ready for the next chr
    loop delays are irrelevant  
    #11
    xfiles_2007
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    Re: External clock sync 2019/09/28 06:53:17 (permalink)
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    hmmm not sure what it is...
     
    just sending a constant set of 0xAA but after some time there seems to be some corruption or additional packet after the 0xAA..
     
    The clock is varying on the receiving end.... not sure how to counter this or check it so I can send the byte on the right phase
     
    https://ibb.co/DtTRxVj
    https://ibb.co/Dbr43hx
     
     
    #12
    NorthGuy
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    Re: External clock sync 2019/09/28 08:32:46 (permalink)
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    xfiles_2007
    hmmm not sure what it is...



    I don't see any clock slowing on your LA pictures.
     
    The first picture has a spurious character, which is either noise or a bug in your code.
     
    The second picture, I have no idea what it's of.
    #13
    xfiles_2007
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    Re: External clock sync 2019/09/28 08:47:20 (permalink)
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    the code is just a loop of sending 0xAA with a delay after it.... but yea this noise just randomly appears.
     
    The second picture is the clock - its varying pulses ? like 2 normal then 1 long - Im no expert with the clocks but its like that.
     
    #14
    xfiles_2007
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    Re: External clock sync 2019/09/28 10:15:59 (permalink)
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    Is there a way I can pickup the noise in software - catch it and throw it away ?

    So send a byte - detect if there’s some incoming noise and discard it and carry on ?
    #15
    NorthGuy
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    Re: External clock sync 2019/09/28 11:50:06 (permalink)
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    xfiles_2007
    The second picture is the clock - its varying pulses ? like 2 normal then 1 long - Im no expert with the clocks but its like that.



    Incoming clock to your PIC? What frequency it is supposed to be? 5 MHz?
     
    Where did you take this signal from? What's the sample rate of your LA? 12 MHz? It's too low of a frequency to capture 5 MHz signal correctly. You need 50 MHz or more.
     
    To see the nature of the noise you need an analog scope. Try making wires shorter and connections better.
    #16
    ric
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    Re: External clock sync 2019/09/28 23:50:56 (permalink)
    +2 (2)
    I'd like to see ALL the code that is being used for this test.
     

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    #17
    xfiles_2007
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    Re: External clock sync 2019/10/11 05:23:33 (permalink)
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    Hi here's the code I have
     
    the baud rate works good. As I said every now and then the receiving device throws back an FF or some kind of corruption/noise some where. 
     
    How can I catch that and handle it ? 
     
    #include <xc.h>
    #include <stdio.h>
    #include <stdlib.h>
    // CONFIG1H
    #pragma config FOSC = ECMP // Oscillator Selection bits (Internal oscillator block)
    #pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
    #pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
    #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
    // CONFIG2L
    #pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
    #pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
    // CONFIG2H
    #pragma config WDTEN = OFF // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
     
    #pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

    #define _XTAL_FREQ 4500000UL
    #define RCSTA_DEFAULT 0x90
    #define TXSTA_DEFAULT 0x20
    #define NINE_BITS 0x40
    #define SPEED 0x4
    #define RX_PIN_RC TRISC7 // I/O RC
    #define TX_PIN_RC TRISC6 // I/O RC
    #define RX_PIN_PI TRISB7 // I/O SC
    #define TX_PIN_PI TRISB6 // 1/O SC

    void PIC_Init(void)
    {
    ANSELA = 0;
    LATA = 0;
    TRISA = 0;
    ANSELB = 0;
    LATB = 0;
    TRISB = 0;
    ANSELC = 0;
    LATC = 0;
    TRISC = 0;

    TRISE &= 0xF8;
    // Set the direction of the transmit/receive and flow control bits.
    TRISCbits.TRISC6 = 1; //the transmit bit - MUST BE SET TO 1, then USART controls input output
    TRISCbits.TRISC7 = 1; //the receive bit - MUST BE SET TO 1, then USART controls input output
    TRISBbits.TRISB6 = 1; //the transmit bit - MUST BE SET TO 1, then USART controls input output
    TRISBbits.TRISB7 = 1; //the receive bit - MUST BE SET TO 1, then USART controls input output
    ADCON0 = 0; // Turn off ADC, but setup the TAD
    ADCON1 = 0; // clock so the simulator is happy.
    ADCON2 = 0x0C; // Set ACQT for 2 TAD, set TAD for FOSC/4

    SPBRG1 = 0x15;
    RCSTA1 = (NINE_BITS|RCSTA_DEFAULT);
    TXSTA1 = (SPEED|NINE_BITS|TXSTA_DEFAULT);
    SPBRG2 = 0x15;
    RCSTA2 = (NINE_BITS|RCSTA_DEFAULT);
    TXSTA2 = (SPEED|NINE_BITS|TXSTA_DEFAULT);


    }

    #define RX_PIN_RC TRISC7 // I/O RC
    #define TX_PIN_RC TRISC6 // I/O RC
    #define RX_PIN_PI TRISB7 // I/O pi
    #define TX_PIN_PI TRISB6 // 1/O pi

    int calcEvenParityBit(unsigned par, unsigned width) {
    while (width > 1) {
    par ^= par >> (width/2);
    width -= width/2;
    }
    }

    void TransmitUart1(unsigned char byte)
    {
    TX9D1 = !calcEvenParityBit(byte,8);
    TX1REG = byte;
    //Enable for transmit
    TXEN1 = 1;
    while( !TXSTAbits.TRMT ) //wait for Tx Complete
    Nop();
    //Disable transmit
    TXEN1 = 0;
    while(!PORTCbits.RC7);


    while(1) // remove rx data recvd from our Tx line
    {
    BYTE temp;
    if( PIR1bits.RCIF )
    {
    temp = RC1REG;
    }
    else
    break;
    }
    }

    void delayUS(int value)
    {
    for(int x = 0; x< value; x++)
    NOP();

    }

    void main(void) {

    PIC_Init();

    TXEN1 = 1;
    TX_PIN_RC = 1;

    while(1)
    {
    TransmitUart1(0xAA);
    delayUS(500);
    }
    }
    #18
    pcbbc
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    Re: External clock sync 2019/10/11 06:31:28 (permalink)
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    Read the received byte from the transmitting end.  If its 0xFF, do something?
    #19
    Jerry Messina
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    Re: External clock sync 2019/10/11 06:42:42 (permalink)
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    //Disable transmit
    TXEN1 = 0;

    Why are you enabling and disabling the transmitter?
     
    How are the uarts connected in your setup?
     
    #20
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