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Hot!External clock sync

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1and0
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Re: External clock sync 2019/10/15 08:18:59 (permalink)
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pcbbc
Transmit and receive can happen at the same time. So no need to disable, and therefore no need for a pull up if you leave tx enabled. With tx enabled the UART has control of the pin and will automatically pull high when nothing to transmit.

The datasheet states the TRIS bits for both RX and TX pins to be set to '1' (input), and that the UART will automatically reconfigure the pin from input to output as needed.  So when it is not transmitting, is the TX pin high impedance?
 
Edit: Or, is turning on the transmitter (TXEN = 1) configures the TX pin to output high?
 
Edit2: RTFM to myself. ;)  TXEN = 1 enables the transmitter; SPEN = 1 enables the UART and automatically configures the TX pin as an output.
post edited by 1and0 - 2019/10/15 09:05:34
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ric
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Re: External clock sync 2019/10/15 12:34:54 (permalink)
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1and0
Edit2: RTFM to myself. ;)  TXEN = 1 enables the transmitter; SPEN = 1 enables the UART and automatically configures the TX pin as an output.

I agree, that is what the datasheet says.
I think it's worth actually testing though. All the PIC16F devices I've played with actually control the TX pin output enable with TXEN too.
I don't see how you could correctly implement half-duplex if it works how the datasheet says, as you can't disable the TX pin without clearing SPEN.
 
Update: I can see now that all the "enhanced midrange" datasheets I have checked contain the same wording. The older midrange datasheets specifically state that the TX pin reverts to high impedance when TXEN is cleared. I'll check what my enhanced parts really do when I get a chance.
 
post edited by ric - 2019/10/15 12:45:14

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Re: External clock sync 2019/10/15 12:56:25 (permalink)
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ric
 
I don't see how you could correctly implement half-duplex if it works how the datasheet says, as you can't disable the TX pin without clearing SPEN.

The 18F24K22 also states when the receiver or transmitter is not enabled then the RX and TX pin may be used for general purpose I/O.
 
So, in either case, I think half-duplex is possible.  It's easier when TX is not disabled, as pcbbc said.
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NorthGuy
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Re: External clock sync 2019/10/15 17:30:19 (permalink)
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xfiles_2007
One wire from I/O of the reader to the rx1 and tx1



Connect TX to I/O through a series resistor (1k or something) and connect RX to I/O with a straight wire. This way you can transmit (when their transmitter is disabled) and receive (at all times) without changing any settings. You will receive everything you transmit, which may be a good thing because you can verify that the transmission was Ok and didn't clash with the peer.
 
However, I would guess when TXEN = 0, the UART module releases the TX pin. Very easy to verify this.
 
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xfiles_2007
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Re: External clock sync 2019/10/15 17:56:29 (permalink)
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Nice suggestion. Will give it a go! 
As mentioned the code i had works but eventually has some noise or so. I'll try to keep the settings static , less chance of noise/clashes :)
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NorthGuy
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Re: External clock sync 2019/10/15 18:17:15 (permalink)
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xfiles_2007
As mentioned the code i had works but eventually has some noise or so.



Probably already said before, but when you float both ends of the wire (as you might do when switching direction) it may go anywhere, hence the probability of glitches and 0xff characters.
 
With the series resistor on one wire, it is always deterministic.
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Re: External clock sync 2019/10/15 21:34:16 (permalink)
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From your other thread, I thought you have it working three years ago. Anyway, here is what I'd do and it's similar to what NorthGuy suggested.
 

Hardware:
  •  connect RX to IO of the reader
  •  connect TX to IO with a series resistor

Setup:
  •  setup RX and TX pins for input (TRIS = 1), as stated in the datasheet
  •  setup baud rate generator
  •  setup for asynchronous operation (SYNC = 0)
  •  setup and enable receiver (CREN = 1)
  •  setup and enable transmitter (TXEN = 1)
  •  enable UART (SPEN = 1) which reconfigures TX as an output and pulls up the RX line

When you want to transmit:
  •  optional, turn off the receiver (CREN = 0) so you don't receive your own data
  •  transmit your data
  •  turn on the receiver (CREN = 1) when you finish transmitting

When you want to receive:
  •  just listen for incoming data
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Re: External clock sync 2019/10/15 21:45:46 (permalink)
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many thanks for the replies. I'll try these things.
 
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ric
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Re: External clock sync 2019/10/15 21:52:56 (permalink)
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1and0
...
 turn on the receiver (CREN = 1) when you finish transmitting

n.b.
"When you finish transmitting" is indicated by TRMT going high.
TXIF will go high before the last byte has been sent.
 

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Re: External clock sync 2019/10/15 22:15:03 (permalink)
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When you want to transmit:
  • optional, turn off the receiver (CREN = 0) so you don't receive your own data
  • wait for TXREG to empty (TXIF = 1) before starting transmission by loading data to TXREG
  • when transmission is finished (TRMT = 1) turn back on the receiver (CREN = 1)
#50
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