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AnsweredHot!Vcore regulator latch-up in PIC24FJ128GA306 !?

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Hansl
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2019/09/22 11:46:56 (permalink)
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Vcore regulator latch-up in PIC24FJ128GA306 !?

I'm currently investigating a weird start-up problem in a battery-powered device using a PIC24FJ128GA306:  If a deeply drained battery (3.6 V lithium cell) is replaced, having a remaining voltage of about 1.2-1.5 V, quite often the PIC won't start up again.  Not even a MCLR will kick it to life again, one has to disconnect the battery, short-circuit the connections to get the remaining Vdd well below 0.5 V — then inserting the battery will start the PIC up again more reliably. 
 
Inserting a battery will naturally cause quite some bouncing at Vdd; on the attached oszillogram I simply connected a 3.1 V power supply with 2.2 Ω series resistance with alligator clips, causing such bouncing.  I have now noticed that on the first rise of Vdd the Vcore regulator delivers its nominal 1.8 V — but when Vdd dips again below 1.8 V, Vcore will track it quite tight downwards… and then upwards to 3-3.6 V Vdd !!  So, the core gets a much too high voltage and doesn't work, little wonder.  At least it isn't damaged, either.  Obviously this seems to be a latch-up of the Vcore regulator.  Which looks to me like a quite bad analog design. 
Vcore is buffered with the recommended 10 µF ceramic cap; Vdd is buffered with 0.1 µF at every pin and another 10 µF ceramic. 
 
==> Is this a known problem?  What am I to do to avoid this?  Activating BOR seems to alleviate the problem, but reliably?  And costs battery life.
 
Thank you very much, Hans
 
 

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Nikolay_Po
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Re: Vcore regulator latch-up in PIC24FJ128GA306 !? 2019/09/22 15:41:25 (permalink) ☼ Best Answerby Hansl 2019/09/23 01:19:29
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It is rather bad situation! I just checked for POR re-arm voltage threshold, DC16 VPOR parameter of TABLE 32-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS of the datasheet. And know what? It is VSS minimum! We are lucky they aren't ask us to apply negative voltage to VDD pin to guarantee power-on reset!
Usually, irrespective of voltage regulators, you had to lower the VDD deeper than VPOR to ensure the PIC will startup correctly at next supply voltage rise. But VPOR=VSS is a nonsense! Very bad. This parameter requires you to short supply voltage to the ground before voltage re-apply.
Minimum voltage the chip can keep a good state is 1.9V while sleeping and 2V while running (DC10, DC12). If you have got down below that, you should short VDD to ground and only after to apply a voltage again.
 
Have you red an Errata? #13:
Module: Power-on Reset When the device is operating with Brown-out Reset (BOR) disabled, it is recommended to follow the data sheet specification of starting the VDD from VSS to ensure an internal Power-on Reset. Failing to do so may result in the device failing to start up or other unexpected behavior. Work around There are three work arounds to resolve the issue: 1. Enable the BOR to ensure that the device gets a proper Power-on Reset. 2. If the BOR cannot be enabled, always start the VDD from VSS to ensure a proper Poweron Reset (Parameter No. DC16 in Table 32-3 of Section 32.0 “Electrical Characteristics” in the data sheet). 3. Use an external voltage supervisor chip on the MCLR pin to hold the MCLR low when the power supply voltage is between 1.4V and 2.0V. Release MCLR after the VDD is in the operating range.

 
Have you tested #1 and #3 workarounds? Also #11 errata may be relevant.
 
As for hardware workaround I'd try to decouple the Vdd from bouncing battery contacts by a diode. And, may be, place some more capacitance at VDD to ground. Probably, a diode in conjunction with larger capacitor will provide single voltage rise at VDD without of several rather sharp deeps as on your scope diagram.
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Hansl
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Re: Vcore regulator latch-up in PIC24FJ128GA306 !? 2019/09/23 01:59:12 (permalink)
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Nikolay, thank you for pointing me to that erratum #13 — I hadn't noticed it, my bad, and it adresses exactly my problem. 
 
For the already existing older hardware, only workaround 1 (BOR) is applicable and it seems to help.  I have to test it further though, whether activating BOR really inhibits this hardware regulator latch-up — if not, it won't help, I'm afraid, since MCLR also cannot reset a latched-up regulator. 
In an already existing redesign, a large ultracap was added to Vdd which should suppress bouncing.  But on the other hand it holds Vdd much longer in the dangerous region.  In that redesign, a MCP121 was also added for external MCLR — I will test that hardware too, if MCLR without BOR does inhibit the latch-up. 
 
There is another dubious parameter in the data sheet, DC17 (SVdd) in the same table 32-2:  Vdd minimum rise rate 0.05 V/ms — this was my motivation to add the MCP121, since Vdd will rise only slowly with a large cap and a weak battery.  This parameter should have made also me suspicious about bouncing Vdd! 
 
DC17, Vpor, I had seen and considered and thought it silly:  it specifies that Vdd must be no less than Vss (not negative) for POR to work.  It does not specify an upper limit though, how high Vdd may be at most for POR to work.  Only the erratum #13 clarifies that Vdd should start really from Vss up.  And workaround 3 suggests that MCLR should work if issued and held while Vdd still <1.4 V… I'll see whether it inhibits latch-up and is immune to bouncing. 
 
Another thing we will have to look into is oscillator switching:  only POR and BOR do reset it to initial configuration.  MCLR leaves the oscillator in possibly different current mode!  (Table 7-2). 
 
Thank you, Hans
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