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AnsweredHot!PIC16F1508 CLC3 & EUSART Tx pin conflict?

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JDW
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2019/09/17 01:44:26 (permalink)
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PIC16F1508 CLC3 & EUSART Tx pin conflict?

My problem is that the RB7 pin output of my 4-input AND using CLC3 isn't what is expected.  I am using the 4-input AND gate as follows:
 
Tx_out (EUSART) = LCx_in[12] = lcxd3 --> lcxg1
C1OUT_sync = LCx_in[2] = lcxd4 --> lcxg4 (invert)
 
lcxg1 -----|&&&&&&
lcxg2 ----o|            & _____ lcxq (CLC3, RB7)
lcxg3 ----o|            &
lcxg4 ----o|&&&&&&
 
Expected Functionality: When both Tx_out and C1OUT_sync are HI, the CLC3 output should be HI, and if either input goes LO, the output should also go low -- the output being on the RB7 pin.  (C1OUT_sync is normally LO, so I invert it as an input to the AND gate.  Also note that lcxg2 and lcxg3 are not used, so they must be inverted so they are always HI.)
 
Actual Functionality (PROBLEM): RB7 is always HI even when C1OUT_sync goes LO. (I can test this by putting Comparator1's output on RA2 and watching it on my scope along with RB7.)
 
If I don't invert lcxg2 or lcxg3, then RB7 is always LO.
If I don't invert lcxg4 (C1OUT), then RB7 is always LO.
 
So it seems that Tx_out is controlling the RB7 pin.  I don't know what other explanation there is.  According to the 16F1508 datasheet, Tx-out of the EUSART and the CLC3 output share the same pin -- RB7.  However, TABLE 11-5 on page 112 of the datasheet says that CLC3 has priority over TX.  So TX shouldn't be taking over control of RB7.  CLC3 should have priority.
 
Here's the relevant code:
 
 banksel  PORTA       ; [Bank 0] Clear all Ports.
 movlw    b'00100010' ; Set PORTA Initial States. RA1 & RA5 are normally HI.
movlw    PORTA
clrf     PORTB       ; PORTB Initial States are all normally LO.
movlw    b'00000010' ; Set PORTC Initial States. RC1 is normally HI.
movwf    PORTC
banksel  LATA        ; [Bank 2] Clear all data Latches.
clrf     LATA
clrf     LATB
clrf     LATC
movlw    b'11000100' ; Enable VFR=1.024v & Comparator Buffer
movwf    FVRCON
; NOTE: LoPWR Sleep = OFF (VREGPM=0), so FVR is stable on exit from RESET.
movlw    b'11100111' ; Enable Comparator1. C1VP>C1VN(non-inverted). Sync->TMR1-CLK.
movwf    CM1CON0     ; C1OUT enabled. C1POL=0. Normal PWR. Hysteresis ON. ASYNCH.
movlw    b'00100011' ; bits 5-4: C1VP connects to FVR Voltage Reference
movwf    CM1CON1     ; bits 0-2: C1VN connects to C1IN3- pin (RC3)
movlw    b'00000100'
movwf    CM2CON0     ; Disable Comparator2 module. Normal/High Speed.
movlw    b'00000010' ; bits 0-2: C2VN connects to C2IN2- pin (RC2)
movwf    CM2CON1
; We will use external pull-ups so disable the internal ones.
banksel  WPUA        ; [Bank 4]
clrf     WPUA        ; Disable RA0 to RA5 pull-ups individually
clrf     WPUB        ; Disable RB4 to RB7 pull-ups individually
banksel  OPTION_REG  ; [Bank 1]
movlw    b'10000111' ; Disable Internal Pull-ups, TMR0 Prescaler = 1:256
movwf    OPTION_REG  ; (Use 100k external pull-ups instead!)
; Use CLC to "AND" PIC UART Tx_out with Comparator1out so that Tx_out will go to 0
;  when Comparator1out=1.
; CLC "4-input AND" Gate ("o" = inverted):
; lcxg1 (GATE 1 out)───|&&&&&
; lcxg2 (GATE 2 out)──o|&     & ___ lcxq
; lcxg3 (GATE 3 out)──o|&     &
; lcxg4 (GATE 4 out)───|&&&&&
; IMPORTANT!!! You must INVERT outputs of all unused GATES using CLC3POL.
banksel  CLC3CON     ; [Bank 30]
clrf     CLC3CON     ; Disable CLC3. (enable it later)
movlw    b'11000100' ; LCx_in[12]* (Tx_out) is selected for lcxd3 and
movwf    CLC3SEL1    ; LCx_in[2]* (C1OUT_sync) is selected for lcxd4.
banksel  ANSELA      ; [Bank 3] Make PORTA & PORTB DIGITAL I/O.
clrf     ANSELA      ; PORTA = Digital I/O.
clrf     ANSELB      ; PORTB = Digital I/O.
movlw    b'00001101' ; RC0=Comparator2-IN(+), RC2=Comp2-IN(-), RC3=Comp1-IN(-)
movwf    ANSELC      ; PORTC = Mixed Analog & Digital I/O.
; NOTE! Set unused pins to Outputs and make them LO! (NOTE: MCLR/RA3 is Input-only!)
; But set all Analog pins to INPUTS (whether those analog pins be inputs or outputs).
banksel  TRISA       ; [Bank 1]
movlw    b'00110010' ; RA2=Comparator1out. RA1, RA4, RA5 are Digital Inputs.
movwf    TRISA       ; PORTA I/O setup
movlw    b'00100000' ; Make RB5/Rx an input. (RB7/Tx and the rest are outputs.)
movwf    TRISB       ; PORTB I/O setup
movlw    b'00001101' ; RC0=Comparator2-IN(+), RC2=Comp2-IN(-), RC3=Comp1-IN(-)
movwf    TRISC       ; RC4 & RC1 are LED outputs & RC6 is the Relay output.
banksel  CLC3GLS0    ; [Bank 30]
movlw    b'00100000' ; lcxd3T (T=not inverted) (Tx_out) is gated into lcxg1
movwf    CLC3GLS0    ; (See CLC3SEL1 above for lcxd3T definition.)
clrf     CLC3GLS1    ; nothing gated (lcxg2) -- invert in CLC1POL
clrf     CLC3GLS2    ; nothing gated (lcxg3) -- invert in CLC1POL
movlw    b'01000000' ; lcxd4N (N=inverted) (C1OUT_sync) is gated into lcxg4
movwf    CLC3GLS3    ; (See CLC3SEL1 above for lcxd4N definition.)
movlw    b'00000110' ; Invert outputs of these GATES: lcxg2 & lcxg3
movwf    CLC3POL     ; (NOTE: No inputs on unused gates makes their output 0.)
; * See TABLE 24-1 on pg.258 of the 16F1508 datasheet for more info on LCx_in[].
movlw    b'11000010' ; Enable CLC3, Enable CLC3 output pin, Set "4-input AND".
movwf    CLC3CON
; Default BAUD rate of Fingerprint Sensor: 9600, 8-bits, no parity bit, 1 Start/Stop bit
; NOTE: 16-bit Baud Gen. & Hi-spd Asynch yields a low -0.08% error (9592 baud) @16MHz.
banksel  BAUDCON     ; [Bank 3]
movlw    b'01001000' ; Disable Auto-Baud, non-inverted data to Tx pin,
movwf    BAUDCON     ; 16-bit Baud Rate Generator, Disable Auto-Wake
; 16F1508 datasheet p.240, SPBRGH:SPBRGL = d'416' (Fosc=16MHz)
; 416 = 00000001 10100000
movlw    b'00000001' ; Load SPBRG value for 9592 Baud, @Fosc=16MHz.
movwf    SPBRGH
movlw    b'10100000'
movwf    SPBRGL
; NOTE: When SPEN=1, Tx & Rx pins go HI.
movlw    b'10000000' ; Serial port SPEN(b7) enabled, 8-bit, CREN(b4)=0
movwf    RCSTA       ; (CREN=0 disables EUSART "Receive" for now)
movlw    b'00100110' ; High-speed Asynch enabled, SYNC(b4)=0
movwf    TXSTA       ; [TXEN (bit 5) = 1: transmit enabled]

 
Any kind help you can provide would be greatly appreciated.
 
Thank you.
#1
pcbbc
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 01:55:53 (permalink)
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This is pointless...
banksel  PORTA       ; [Bank 0] Clear all Ports.
 movlw    b'00100010' ; Set PORTA Initial States. RA1 & RA5 are normally HI.
movlw    PORTA

...if you are then going to do this...
banksel  LATA        ; [Bank 2] Clear all data Latches.
clrf     LATA

RA1 and RA5 are now low.
#2
JDW
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 02:39:34 (permalink)
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pcbbc
This is pointless...



Thank you for pointing that out, but I assure you that is not the root problem.  If you have specific thoughts as to the root problem, I am all ears! :-)
#3
ric
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 03:42:15 (permalink)
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JDW
...
If I don't invert lcxg4 (C1OUT), then RB7 is always LO.

Doesn't this mean that the CLC is controlling RB7?
If the EUSART was, then you shouldn't be able to change RB7 just by changing the CLC configuration.
 
post edited by ric - 2019/09/17 03:46:41

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#4
JDW
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 05:18:04 (permalink)
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ric
Doesn't this mean that the CLC is controlling RB7?
If the EUSART was, then you shouldn't be able to change RB7 just by changing the CLC configuration.



Sure seems so, doesn't it?  Yet it still doesn't work right, like I said...
 
PROBLEM: RB7 is always HI even when C1OUT_sync goes LO. (UNLESS I deliberately program the C1OUT input to the CLC3 AND gate to NOT be inverted, in which case RB7 then is LO and stays LO forever, regardless of the state of C1OUT.)
 
Comparator1 is just an OP-AMP with one input internally connected to FVR=1.024V and the other input connected to a pin that in turn is connected to an external voltage divider resistor pair.  The output of Comparator1 is normally LO and drives a PNP transistor through a 470ohm base resistor, which is normally ON because Comparator1_OUT is normally LO.  But when the PIC's input voltage falls below the threshold voltage set by the voltage divider (below 2.84v, with 3.3v being the nominal voltage), then Comparator1_out goes HI and turns off the PNP.  
 
The reason I need to run Tx through CLC3 is because I want Tx to automatically drop from HI to LO when the PNP shuts OFF, without any interrupts or code intervention.  Theoretically that should work.  Anyway, the reason is because the PNP kills power to my external fingerprint sensor, and if I only kill its power but leave Tx HI, then the sensor doesn't fully power down.  I need to kill Vin to the sensor with the PNP and make Tx_out (RB7) LO too, at the same time.
 
That's why I am using an AND gate with CLC3.  CLC3 is the only CLC of the 4 which allows me to have C1OUT and Tx_out as inputs to an AND gate.   And I need to invert Comparator1 Output at the AND gate input because Comparator1 Output is normally LO and that LO would keep the gate from changing state when Tx needs to send data. Tx is normally HI so the CLC3 AND gate output needs to be normally HI too.  I also need to invert the 2 unused pins because if I don't, those inputs would be LO all the time and prevent the AND gate from changing state.
 
What I want to happen is when Comparator1 Output goes HI, that input to the CLC3 AND gate will be invert to LO and which should trigger a change of state on the AND gate output from HI to LO -- putting that LO on the RB7 pin, which is basically killing Tx like I want.  The problem is that the CLC3 AND gate output (RB7) stays HI!  RB7 stays HI even though Comparator1 Output is HI (inverted to LO at the AND gate)!  And for the life of me I cannot see why.  That's why I created this thread because the solution escapes me.  
 
If you check my code, you'll see I've set it up as described.  But perhaps there's a tiny error in it somewhere I am not seeing.  I've been over it dozens of times, but I am not seeing what's wrong here.
#5
ric
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 05:36:09 (permalink) ☼ Best Answerby JDW 2019/09/17 19:55:01
+1 (1)
Here
 movlw    b'11000100' ; LCx_in[12]* (Tx_out) is selected for lcxd3 and
 movwf    CLC3SEL1    ; LCx_in[2]* (C1OUT_sync) is selected for lcxd4.



You have the bits for lcxd4 in the wrong position.
b'11000100' should be
b'01100100'
 

I also post at: PicForum
Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
NEW USERS: Posting images, links and code - workaround for restrictions.
To get a useful answer, always state which PIC you are using!
#6
JDW
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Re: PIC16F1508 CLC3 & EUSART Tx pin conflict? 2019/09/17 19:55:52 (permalink)
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ric
 
You have the bits for lcxd4 in the wrong position.
b'11000100' should be
b'01100100'
 

 
Thank you, Ric.  That fixed the problem!
#7
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