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2005/08/31 19:14:04 (permalink)



Hello Everybody.

We are starting this thread (russeld and me) as a SCL Primer, to fill the gap on the lack of documentation in the current version of the IDE for those who want to use the SCL language in MPSIM Simulations.
This primer is intended to be a structured exploration of what we know currently of the SCL language: what it is and what it is not, its current capabilities and limitations.

Mainly we want to cover the basics of the SCL language so everyone can use it. It is a well structured, self-documented high-level language, and is simple enough to use without a steep learning curve.

The posts will cover the contents of a 'flash course' on SCL, without the strong commitment of being authoritative or even a manual of the language, since it is undocumented. We will try to present clearly the structures and concepts in an incremental fashion, and offer working SCL code, for all who are interested to download and test the concepts.

Our main objective in doing this is to get more people involved in using the SCL script language, and create a critical mass to secure this feature in the IDE, eventually getting development attention from Microchip to continue developing SCL, since we feel it is not yet totally implemented.
To make it short, we are trying to get the Genie out of the bottle before the cork is put back on.

The 'agenda' for this SCL primer will be:

  • Simulation possibilities with SCL
  • SCL as stimulus generator for MPSIM
  • SCL is derived from VHDL.
  • concept of simulation delta time
  • General structure and syntax.
  • signals
  • variables
  • signal assignments vs. variable assignments
  • processes
  • sequential execution inside processes
  • flow control (if, loop)
  • sensitivity lists
  • the wait statement (wait on, wait until, wait for)
  • parallel execution of processes
  • File operations
  • Report
  • Assert
  • process re-use
  • Using parallel processes to simulate various blocks of external hardware / peripherals.

Since this is a part-time effort, I ask for your patience.
We will post here as time allows.

This primer is neither official nor sanctioned by Microchip. It's an entirely independent effort. Content may be incorrect respecting the actual SCL implementation. Please forgive the authors for any errors. We will try to correct any mistakes found.
The contents of this tutorial is based in the IEEE VHDL Language Reference Manual, The VHDL Cookbook by Peter Ashenden, and direct testing of the SCL environment.
Any comments / feedback / corrections are welcome, but please use the SCL Primer feedback instead, to preserve easy reading for those interested in following this primer.

SCL Undocumented HELP file
A help file containing a cross-reference of all VHDL and SCL language elements, with formal descriptions and examples is attached at the end of this post. The help file was compiled to be used as a quick-reference of the undocumented SCL language. Currently at v0.65.
>>> I have temporarily taken the help file from the public area to correct some errors. Will re-post shortly
post edited by KajitaJ2 - 2006/01/31 09:56:19

6 Replies Related Threads

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    RE: SCL PRIMER / TUTORIAL 2005/09/01 07:48:06 (permalink)

    Software simulation is an important step on firmware development. It allows us to have a controlled environment to verify code behaviour.
    We can step through our program, watch variables, setup input parameters, run a small section.
    But microcontroller code is very often about controlling and processing external circuitry.
    The program sets/clears device pins and work on the external circuit's response.
    There are sensors that must be read and handled.
    There can be user actions that need detection and processing.
    The code may need to decode data encoded in a certain hardware low-level protocol.
    Sometimes a function is divided between external logic and internal program behaviour.

    The simulator, to cope with off-chip activity simulation has the capability to generate and inject Stimulus.
    MPSIM has the Stimulus Controller and the SCL Workbook Generator to manage the creation of syncrhonous and asynchronous stimuli.
    The SCL generator creates a program to execute the actions specified in the workbook (an SCL program), and writes it to a SCL program file.
    When this SCL program is attached to the Stimulus Controller it runs synchronous with the PIC machine code that is being simulated.
    The MPLAB IDE online help covers creation of stimulus scripts using the SCL workbook.
    It's a powerful tool, that allows generation of complex timing waveforms and complex triggering of waveform stimulus.

    With it, for example, you can generate a video sync waveform, feed it to a pin and have it triggered 50µs after a certain value is written to TRISC.

    From the point of view of the SCL program, the PIC is a state machine which signals can be manipulated at will between one clock and the next.
    Since SCL is a programming language, it can go beyond waveform injection and triggering: it can perform algorithmic interaction with the PIC program and emulate external responses and circuit behaviour.
    But the SCL generator will not create such algorithmic behaviour: hand-written SCL programs will.

    With hand-written SCL programs you can inject specialized stimulus from user-supplied text files, simulate onboard circuitry, test and verify program logic glitches (key bounce, invalid states, response time) and report errors, create simulation vectors difficult to have in benchtop testing, generate analog waveform inputs, emulate low-level encoders (Mancester, FSK, PPM) for RF links, all within the controlled environment of MPSIM.

    This primer will not handle SCL generation using the Workbook.
    We will focus on the SCL language, its syntax and constructs, to allow interpretation of any SCL program, hand-written or machine-written.
    < Message edited by j_doin -- Sep. 8, 2005 8:02:17 PM >
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    RE: SCL PRIMER / TUTORIAL 2005/09/04 23:03:48 (permalink)

    SCL is a language (probably compiled to pentium code), used to write MPSIM extensions that alter the simulator state. VHDL (stands for Very hi-speed IC Hardware description language) is a powerful systems description language, used to represent parallel combinatorial logic and sequential logic, design hierearchy and accurate temporal behaviour of logic state assignment. VHDL is used for design and verification of complex VLSI designs, such as processors and large digital systems. It is used for ASIC silicon synthesis and FPGA circuit synthesis and simulation.

    The syntax and structure of SCL is very similar to VHDL, although with some important differences.
    It looks like SCL implements a subset of VHDL oriented for behaviour modelling, while important VHDL characteristics used for hardware synthesis and design hierarchy are left out.
    But SCL retains much of VHDL coding style, concepts, parallel processing, and syntax to be called a VHDL-derived language. Predefined types and subprograms, language packages, are substantially the same as in VHDL. You can almost always use the VHDL reference for the parts of the language that are implemented.

    Moreover, the simplifications of SCL (the parts that are left out) make it a fairly simple language to learn. And the parts that it inherits from VHDL make it a remarkably solid framework for system simulation.


    The MPSIM simulator has a minimum time resolution that is the instruction cycle. Even though real instructions have internal microcycles defined as Q-cycles (4 Qcycles per instruction), MPSIM does not simulate internal Q-cycle activity. The instruction cycle is 4*Tclk, derived from the oscillator frequency, defined in the Simulator Trace window.
    Any event that is smaller than 1 instruction cycle (1 ic) cannot be detected or simulated by MPSIM.
    The SCL program runs each simulation cycle, and all processes are updated at each instruction cycle.
    All signals assigned at a given cycle are updated at the same cycle.


    The SCL language has many lexical elements familiar to high-level languages like Modula2 and ADA. It is derived directly from VHDL and many elements have the same formal implementation. There are some important differences from VHDL, like conditional comparison and case sensitivity, implemented like the C language.
    The Lexical Elements defined in SCL are:

    Comments in SCL can be preceded by the C double slash //, or the VHDL double hyphens --. These two forms are interchangeable, and can be anywhere in a line. All chars from the comment prefix to the endline are considered as comments.

    2.2.2. Identifiers
    Identifiers in SCL are the same as in VHDL. They conform to the following rule:

    identifier ::= letter {[underline] letter_or_digit }
    Identifiers are always case-sensitive.

    2.2.3. Numbers
    Literal numbers may be expressed either in decimal or in a base from 2 to 16. If the literal includes a point, it represents a real number, otherwise it represents an integer. Decimal literals are formally defined as:

    decimal_literal ::= integer [. integer][exponent]
    integer ::= digit {[underline] digit}
    exponent ::= E[+]integer | E - integer
    Some examples are:

    0 1 25 2_5 -- integer literals
    254 2_5_4 25_4 2_54 -- all these represent the same value
    0.0 3.14_15_92_65 5.123E-6 -- real literals
    Based literal numbers are formally defined as:

    based_literal ::= base#based_integer[.based_integer]#[exponent]
    base ::= integer
    based_integer ::= extended_digit {[underline]extended_digit}
    extended_digit ::= digit|letter

    The base and the exponent are expressed in decimal. The exponent indicates the power of the base by which the literal is multiplied. The letters A to F are used as extended digits to represent 10 to 15.
    Some examples:

    2#1100_0100# 16#C4# 4#301#E1 -- the integer 196
    2#1.1111_1111_111#E+11 16#F.FF#E2 -- the real number 4095.0
    2.2.4. Characters
    Literal characters are formed by enclosing an ASCII character in single-quote marks, like:

    'H' 'E' 'L' 'O' 'W' 'R' 'D'

    2.2.5. Strings
    Literal Strings of characters are formed by enclosing the characters in double-quote marks.
    To include a double-quote itself in the string, a pair of double-quotes must be put together.
    Examples of strings:

    "The quick brown fox" "To be or not to be"
    "" -- empty string
    "A ""Rose"" is a Rose, is a Rose" -- contains quote marks

    2.2.6. Binary, Octal and Hexadecimal strings
    SCL provides a convenient way of specifying arrays of bit literals. The formal spec is:

    bit_string_literal ::= base_specifier"bit_value"
    base_specifier ::= B|O|X
    bit_value ::= extended_digit {[underline]extended_digit}
    Some examples:

    B"10001010" -- length is 8
    O"126" -- length is 9, equivalent to B"001_010_110"
    X"A5" -- length is 8, equivalent to B"1010_0101"

    >>> EDITED: moved the SCL.HLP file to the top of this thread.
    < Message edited by j_doin -- Sep. 8, 2005 8:21:15 PM >
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    RE: SCL PRIMER / TUTORIAL 2005/09/05 12:18:49 (permalink)
    2.3. DATA TYPES

    SCL has several predefined data types, and follow the VHDL formal definitions for these predefined types.
    However, user-defined types and subtypes are not available to the user and return "language feature currently not supported".

    The predefined types in SCL include scalar data types and composite data types.
    Scalar types are ordered lists of values, and relational operators are predefined for their values.
    All scalar types fall into one of these: enumeration types, integer types, floating point types, physical types.

    The predefined integer scalar types are:

    integer signed 64bit range
    byte signed 64bit range
    word signed 64bit range

    The predefined enumerated types are:

    type severity_level is (note, warning, error, failure);
    type boolean is (false, true);
    type bit is ('0', '1');
    type character is (
    ' ', '!', '"', '#', '$', '%', '&', ''',
    '(', ')', '*', '+', ',', '-', '.', '/',
    '0', '1', '2', '3', '4', '5', '6', '7',
    '8', '9', ':', ';', '<', '=', '>', '?',
    '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
    'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
    'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
    'X', 'Y', 'Z', '[', '\', ']', '^', '_',
    '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
    'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
    'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
    'x', 'y', 'z', '{', '|', '}', '~');
    type file_open_kind is (read_mode, write_mode, append_mode);
    type file_open_status is (open_ok, status_error, name_error, mode_error);

    The predefined physical scalar types are:

    type time is range <>
    fs; -- femtosecond
    ps = 1000 fs; -- picosecond
    ns = 1000 ps; -- nanosecond
    us = 1000 ns; -- microsecond
    ms = 1000 us; -- millisecond
    sec = 1000 ms; -- second
    min = 60 sec; -- minute
    hr = 60 min; -- hour
    end units;

    type cycle is range <>
    ic; -- instruction cycle
    end units;

    Examples of literals of various types:

    'A' 'B' 'Y' '0' '1' -- character
    '0' '1' -- bit
    false -- boolean
    153.45 us 230_000 ps -- time
    200 ic 35.1 ic -- cycle

    Each type has a set of operations that can be done upon objects of that type. SCL is strongly typed, so operations mixing different types are not allowed.


    Arrays are indexed collections of objects of the same type.
    SCL may use arrays internally to define bitvectors and internal functionality.
    There is no predefined array type visible to the user.

    Records are composite types of possibly different types.
    Record fields are accessed as individual data objects. SCL uses records to define bitfields and config fields for SFRs on the current processor entity.
    Examples of records:

    ADCON0.GO_nDONE -- bit 1 of ADCON0
    ADCON0.ADON -- bit 0 of ADCON0
    < Message edited by j_doin -- Sep. 8, 2005 8:22:43 PM >
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    RE: SCL PRIMER / TUTORIAL 2005/09/06 19:54:21 (permalink)

    A Data object is a named item which has a value of a specified type. There are three classes of objects: constants, variables and signals.

    A constant is an object which is initialised to a specified value in its declaration. Constants cannot be atributed to, only used as part of an expression.

    The formal declaration of a constant is:

    constant_declaration ::=
    constant identifier_list : subtype_indication [ := expression ] ;

    Constant declarations with the initialising expression missing are called deferred constants. SCL does not currently support deferred constants.
    Some examples:

    constant delaytime : time := 30 us;
    constant ACline_period : time := 16.666666666 ms;
    constant timer_init : word := 16#BD50#;

    A variable is an object to which a value can be attributed to.
    Variables have the following formal declaration:

    variable_declaration ::=
    variable identifier_list : subtype_indication [ := expression ] ;

    The initial value expression, if present, is evaluated and assigned to the variable when it is created. If the expression is absent, a default value is assigned when the variable is created. The default value for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the lowest in an ascending range, or the highest in a descending range.
    Some examples of variable declarations:

    variable data_point : integer; -- defaulted to 0000
    variable delaytime : time := 30 us;

    Variable attribution is performed as a sequential operation.
    Consecutive assignments to a variable can be performed in the same simulation cycle.

    Variables and constants can only be declared using the predefined types: bit, boolean, character, string, byte, word, integer, time, severity_level, file_open_kind, file_open_status, line, text.

    SCL is a strongly typed language, and variables can only be attributed to values and expressions of the same base type. Any enumerated or physical type variable requires a literal or data object of the same type. Scalar integer types can be freely mixed in expressions and attributions, so it's perfectly legal in SCL to assign a variable of type word to a variable of type byte.

    Signals are special data objects that represent hardware objects, like PIC registers and bits.
    Signal assignment and expressions follow special rules and will be treated together with concurrent statements.
    < Message edited by j_doin -- Sep. 8, 2005 8:23:17 PM >
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    RE: SCL PRIMER / TUTORIAL 2005/09/08 18:51:06 (permalink)
    +2 (1)
    Sequential statements in SCL follow the same general rules of logical program flow of many high-level languages.
    These statements control the logical flow of a process, and change the order of value assignment to data objects.
    3.1. Variable Assignment
    A value is assigned to a variable following the syntax:

        variable_assignment_statement ::= target := expression;
        target ::= name;
    The target of an assignament is an object name, declared previously. The value of the expression is given to the named object.
    The object and the value must have the same base type.
    Several assignment operations can be done sequentially to the same variable in a given simulation cycle. The variable's value is changed by each subsequent assignment operation.
    Examples of variable assignment:

        data_point := 16#F00#;
        data_point := data_point + 16#00A#;
        counter := counter + 1;
        delay := now;
        delay := delay + 200 us;
    3.2.   Boolean Expressions
    Complex boolean expressions are not currently supported in SCL. Only simple comparison of 2 values, variables, constants, signals or literals of the same type are allowed. The boolean relational operators in SCL are similar to those used in the C language: {==, !=, <=, >=, =}. SCL also accepts the VHDL style for the not equal {/=} relational operator. The only logical operator currently accepted in SCL is the not operator. The logical operators {and, or, nand, nor, xor} are not currently supported.
    3.3.  If Statement
    The if statement controls logic execution of statements depending on one condition. The syntax for if is:

        if_statement ::=
            if <condition> then
            { elsif <condition> then
                sequence_of_statements }
            [ else
                sequence_of_statements ]
            end if;
    The <conditions> are expressions resulting in boolean values. The conditions are evaluated successively until a value true is found. When a true expression is found, the corresponding statement list is executed. If no true condition is found, the else statement list is executed. Nesting of if statements is supported.
    3.4.   Loop Statements
    SCL has a basic loop statement that can be used to form the conditional loop (while .. loop) and the iterated loop (for .. loop).
    The general syntax for the loop statement is:

        loop_statement ::=
            [ iteration_scheme ] loop
            end loop;
        iteration_scheme ::=
            while condition
            | for loop_parameter_specification
        loop_parameter_specification ::= identifier in discrete_range
        discrete_range ::=
            lowest_enumerated_value to highest_enumerated_value
            | highest_enumerated_value downto lowest_enumerated_value

    If the iteration_scheme is omitted, we have the base form of the loop, which will repeat the list of statements forever.
    An example of a basic loop is:

        end loop;

    The while iteration scheme allows a test condition to be evaluated before each loop iteration. The iteration only proceeds if the evaluation is true. If the condition is false, the loop terminates and execution continues on the next instruction following end loop;.
    An example of while loop:

        while endfile(data_file) == false loop
            statements ...;
        end loop;

    The for iteration scheme allows a specified number of iterations. The loop parameter specification declares an object which takes on successive values from the given range for each iteration of the loop. Within the loop, the object is treated as a constant and can be used in expressions as a scalar value, but can not be assigned to. The object has no existence outside the loop.
    An example of iterated loop is:

        for count in 1 to 10 loop
            data_point := data_point + count;
        end loop;

    There are two additional statements that can be used inside a loop to alter the loop iteration pattern: the next and exit statements.
    The next statement skips all statements until the end loop statement and starts the subsequent loop iteration from the beginning.
    The exit statement skips all statements until the end loop and terminates the loop, continuing execution at the statement following end loop.
    The syntax of these two statements is:

        next_statement ::= next [ loop_label ][ when condition ];
        exit_statement ::= exit [ loop_label ][ when condition ];

    If the loop_label is omitted, the statement applies to the innermost loop, otherwise it applies to the named loop.
    If the when clause is present, its condition is evaluated: if true the next/exit is executed, if false execution of the loop continues normally.
    The use of a exit when with a basic loop is equivalent to a loop .. until present in some languages.

    Currently the for iteration scheme, along with the next keyword are not supported by SCL (we hope it will in the future). An similar iterated loop can be construed with the while loop:

        count := 1;
        while count <= 10 loop
            data_point := data_point + count;
            count := count + 1;
        end loop;

    Some examples:

        index := 200;
        while index <= 300 loop
            exit when match(data_line, "") == true;
            index := index + 1;
        end loop;
        while volume < max_volume loop
            exit when idx == 0;
        end loop;
            counter := counter + 1;
            exit when counter >= 10; -- equivalent to loop .. until counter >= 10
        end loop;

    Loops and the if statements are the sequential flow control blocks in SCL. They can be combined and nested to create complex iteration patterns for algorithm modeling.
    >>> edited to highlight the for loops are not supported. (Thanks to brumbarchris for noting this)
    post edited by j_doin - 2006/02/23 14:58:10
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    Notepad ++ 2007/08/01 07:21:38 (permalink)
    Notepad++ offers a VHDL syntax highlighting option that works well for editing *.SCL files. It includes code folding too.

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