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Hot!PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read

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ENRO
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2019/09/16 01:56:08 (permalink)
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PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read

Hi.
I have a weird problem with SPI communication and internal Flash memory used as virtual eeprom. The SPI modules (SPI1 to SPI6) are used to communicate with some engines, and the data that is passing through them, contains speeds and positions of those engines. SPI modules are configured in Master mode, 8 bit combined with DMA, no enhaced buffer. Everything was working perfect until I enabled virtual eeprom memory. The error appeared as disturbing knocks that engines started to make at random time. After some investigation I discovered wrong positions reading . 24-st bit of 32 bit position value was set despite it should be 0 (it changed position from -6.52 to -2.52, for now only SPI6). The weird thing is that error was always caused by these particular bit. After more investigation I find out that error was caused by internal flash read. When I comment out 1 line of code responsible for flash reading, everything started to work as expected. Further investigation let mi discovered, that while error was appearing, MISO line was pulled up by uC and forcing the error. With code for detecting abnormal changes of positions I determined that olny this one bit in 32 bit position changed, but I don't have proof there are no other errors in communication so far.
The code fo reading flash (modified microchip virtual eeprom library):
#define DATA_EE_ADDRESS 0x1D000000
typedef union
{
unsigned int table[NUM_DATA_EE_PAGES][NUMBER_OF_INSTRUCTIONS_IN_PAGE];
} _ee_data_type;
 
_ee_data_type memory_preserver __attribute__((space(prog), address(PA_TO_KVA1(DATA_EE_ADDRESS))));
 
_ee_data_type *eedata_addr; // __attribute__ ((aligned(4096))) - by specifying addr
...
eedata_addr = (_ee_data_type*) PA_TO_KVA1(DATA_EE_ADDRESS);
...
unsigned int dataEEval;
...
// perform flash read - in normal operation of system this line is executed asynchronously when there is free time. Commenting out fix error
dataEEval = eedata_addr->table[currentPage - 1][4 + i];
 

 
SPI initialization:

ENGINE_X_SPICON = 0;
ENGINE_X_SPICONbits.FRMPOL = 0;
ENGINE_X_SPICONbits.MSSEN = 0;
ENGINE_X_SPICONbits.MCLKSEL = 0;
ENGINE_X_SPICONbits.DISSDO = 0;
ENGINE_X_SPICONbits.ENHBUF = 0;
 
ENGINE_X_SPICON2bits.AUDEN = 0;
 
ENGINE_X_SPICONbits.MODE32 = 0;
ENGINE_X_SPICONbits.MODE16 = 0;
 
ENGINE_X_SPICONbits.SMP = 1;
 
ENGINE_X_SPICONbits.CKE = 1;
ENGINE_X_SPICONbits.SSEN = 0;
ENGINE_X_SPICONbits.CKP = 0;
ENGINE_X_SPICONbits.MSTEN = 1;
ENGINE_X_SPICONbits.DISSDI = 0;
ENGINE_X_SPICONbits.STXISEL = 0;
 
ENGINE_X_SPICON2bits.IGNROV = 1;
 
ENGINE_X_SPICON2 = 0;
 
ENGINE_X_SPISTAT = 0;
 
ENGINE_X_SPIBUF = 0;
 
ENGINE_X_SPIBRG = 0;
 
ENGINE_X_SPICONbits.ON = 1;

 
 
Logic analyzer:
main communication.png
Picture 1. 5 engine readings, A, B, D, E - ok, C - error
 
SPI_Z_TIME_-2.PNG
Picture 2. Reading A (time: -2) - ok
Z position: (float)(((int)0xFE5E75F4) / -4194304) = -6.52
 
SPI_Z_TIME_-1.PNG
Picture 3. Reading B (time: -1) - ok
Z position: (float)(((int)0xFE5E75FA) / -4194304) = -6.52
 
SPI_Z_TIME_0.PNG
Picture 4. Reading C (time: 0) - error
Z position: (float)(((int)0xFF5E75FE) / -4194304) = -2.52
 
SPI_Z_TIME_1.PNG
Picture 5. Reading D (time: 1) - ok
Z position: (float)(((int)0xFE5E75FD) / -4194304) = -6.52
 
Has anyone ever had a similar problem?
 
Edit: Why I cant insert image into text?
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post edited by ENRO - 2019/09/16 02:15:20

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#1

22 Replies Related Threads

    friesen
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 06:08:58 (permalink)
    0
    Are you using dma?

    Erik Friesen
    #2
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 06:18:18 (permalink)
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    Yes, I mentioned that.
    #3
    maxruben
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 07:04:29 (permalink)
    0
    Note that the construct:
    ENGINE_X_SPICONbits.bit = 1;
    Is not atomic and not safe to use in ISRs to manipulate bitfields. You should use the CLR/SET/INV offset registers with masks instead.
     
    This goes for registers that can have one or more bits directly changed by the hardware for registers that contain several bits (such as interrupt flags).
     
    This can lead to hard to find bugs since it might just result in a problem at code sequences for very limited time periods. This has to do with the read-modify-write nature of the instructions that resgister.bit=x is translated to.
     
    Note that there is no problem with the code shown in your post above so if your problem is because of this it is in code you have not shown.
     
    /Ruben
     
     
     
     
    #4
    friesen
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 07:19:07 (permalink)
    0
    The first line of review would be your cache management.

    Erik Friesen
    #5
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 14:02:15 (permalink)
    0
    maxruben:
    I'm aware of atomic operations, and what problems can I get when not using them. But as I wrote in first post, when flash reading is disabled, everything works ok, so no atomic access is not a problem. Another thing, is that
    ENGINE_X_SPICONbits.bit = 1;
    is used only on one place, so there should be no problem with read-modify-write instructions executed from different places of code.
    The rest of the code is very large, so posting everything makes no sense. But I my opinion, the is no such future that even if I wanted to could change state of MISO line only for one bit of data. Or am I missing something?

    friesen:
    The first thing I started to check was cache management. But I'm not sure if I tested it the right way.
    When using attributes, I know what to do, but how to control if variable is cached when we use
    __attribute__((space(prog), address(PA_TO_KVA1(DATA_EE_ADDRESS))))
    ? I can't add coherent attribute in this case.
    Is it enough to change desired address from KVA1 to KVA0?
    #6
    ric
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 15:52:57 (permalink)
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    ENRO
    ENGINE_X_SPICONbits.bit = 1;
    is used only on one place, so there should be no problem with read-modify-write instructions executed from different places of code.

    What about accesses to other bits in ENGINE_X_SPICONbits ?
    THAT is the problem.
     
     

    I also post at: PicForum
    Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
    NEW USERS: Posting images, links and code - workaround for restrictions.
    To get a useful answer, always state which PIC you are using!
    #7
    aschen0866
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 22:25:09 (permalink)
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    ENRO
     

    ...
    // perform flash read - in normal operation of system this line is executed asynchronously when there is free time. Commenting out fix error
    dataEEval = eedata_addr->table[currentPage - 1][4 + i];
     


    Can you explain to us what the array indexing [4 + i] is all about? 
    #8
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/16 23:25:34 (permalink)
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    ric
    ENRO
    ENGINE_X_SPICONbits.bit = 1;
    is used only on one place, so there should be no problem with read-modify-write instructions executed from different places of code.

    What about accesses to other bits in ENGINE_X_SPICONbits ?
    THAT is the problem.
     
     


    I'll try to check that.
     
    aschen0866
    ENRO
     

     
     
     
    ...
    // perform flash read - in normal operation of system this line is executed asynchronously when there is free time. Commenting out fix error
    dataEEval = eedata_addr->table[currentPage - 1][4 + i];
     
     
     
     
     
     
     


    Can you explain to us what the array indexing [4 + i] is all about? 


    eedata_addr->table is two dimensional table
    unsigned int table[NUM_DATA_EE_PAGES][NUMBER_OF_INSTRUCTIONS_IN_PAGE];
     so [4 + i] is index of a specific 32-bit instruction in current page of flash
    post edited by ENRO - 2019/09/16 23:28:10
    #9
    maxruben
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/17 09:43:34 (permalink)
    4 (1)
    ENRO
    maxruben:
    Another thing, is that
    ENGINE_X_SPICONbits.bit = 1;
    is used only on one place, so there should be no problem with read-modify-write instructions executed from different places of code.



    As I wrote this exact line isn't your problem but just an example of the register.bit=x construct which (for PIC32s) is translated to several (non-atomic) sequence of instructions.
     
    Change all places of "register.bit=x" in your code to "registerSET=..._MASK" (or registerCLR or registerINV) to make sure that this isn't your problem.
     
    /Ruben
    #10
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/25 05:09:16 (permalink)
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    maxruben
    Change all places of "register.bit=x" in your code to "registerSET=..._MASK" (or registerCLR or registerINV) to make sure that this isn't your problem.
     
    /Ruben


    I've changed all SPI and DMA registers access to use SET and CLR and nothing changed, error is still there
    #11
    maxruben
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/27 09:25:02 (permalink)
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    Do you have any context switching (interrupts) in your code?
     
    /Ruben
    #12
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/30 00:27:34 (permalink)
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    maxruben
    Do you have any context switching (interrupts) in your code?
     
    /Ruben


    1) 10 kHz Timer for system control - interrupt priority 7, subpriority 1
    2) DMA3 interrupt(SPI1,3,4,5,6 with engines error) - priority 7, subpriority 3
    3) DMA6 interrupt(SPI2 communication with another PIC32MZ ) - priority 5, subpriority 3
    4) CHANGE NOTICE interrupt - priority 5, subpriority 0
     
    I know there is a lot of this, but everything was working perfectly until I started reading Flash.
     
    post edited by ENRO - 2019/09/30 00:28:55
    #13
    maxruben
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/09/30 13:32:45 (permalink)
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    Can you show the code for the interrupt handlers?
     
    /Ruben
    #14
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/01 06:09:29 (permalink)
    0
    Which interrupt and which part of code? The interrupt code is quite complex (I'm aware that it should be short, but it isn't, and it's working - I assume not by accident Smile: Smile)
    If you think about SET and CLR registers for ISR flags - yes, I'm using them
    #15
    maxruben
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/01 12:33:30 (permalink)
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    In my experience (all 35 years of it), a lot of problems like the ones you are having are caused by unexpected side effects in interrupt routines and it is kind of hard to give any advice without seeing the code.
     
    /Ruben
    #16
    ENRO
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/02 06:45:25 (permalink)
    0
    I understand that, but how interrupt routines can change hardware state of SDI pin for only one byte?
    I know it is hard to help without the code, but it is really complex, and I'm not sure if I'm allowed to post all of if.
     
    I can post some parts of code or perform some more tests if it helps.
    #17
    friesen
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/02 06:54:31 (permalink)
    5 (1)
    I am rather doubtful this is a silicon bug.  The IC reads its own flash all day long, manually reading flash is not out of the ordinary operations.  Writing flash will probably cause a cpu stall.
     
    However, when memory is getting trashed, anything can happen.  When memory is only slightly trashed, then random things happen.

    Erik Friesen
    #18
    Jim Nickerson
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/02 07:01:39 (permalink)
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    ENRO,
    I take it you have yet to reduce your code to the smallest example that still produces the error ?
     
    #19
    friesen
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    Re: PIC32MZ2048EFH144 rev. A3 SPI disturbed by internal Flash read 2019/10/02 07:20:01 (permalink)
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    Trashed, meaning something like DMA'ing to the peripheral locations.

    Erik Friesen
    #20
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