Confusing language in documentation re "CPU Priority Level" & "interrupt priority level"
The "Sec10. Power-Saving Features" document for PIC24F, in subsection 3 "Instruction-Based Power-Saving Modes", the language is confusing, to me. In section 10.3.1.6 "WAKE-UP FROM SLEEP ON INTERRUPT", talks about interrupts as assigned to a "CPU priority level". But, there is also a CPU priority level, set by the IPL bits [4 in all], which, certainly, is a different thing, than an interrupt priority level, like the Change Notification [CNIP], or the Timer2 Interrupt Priority [T2IP].
So...why does this document use the term "CPU priority", when it seems to be referring to an IPC style interrupt priority?!?
For instance: "User interrupt sources
that are assigned to CPU priority level
0 cannot wake the CPU from Sleep
"To use an interrupt as a wake-up source, the CPU priority level
for the interrupt
must be assigned to CPU priority level
1 or greater."
How can a regular interrupt
have a CPU priority level
?!? Isn't it just a priority level
, and isn't CPU priority
a different thing?
post edited by ReverseEMF - 2019/09/08 07:04:00