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Helpful ReplyHot!Confusing language in documentation re "CPU Priority Level" & "interrupt priority level"

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ReverseEMF
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2019/09/07 22:24:32 (permalink)
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Confusing language in documentation re "CPU Priority Level" & "interrupt priority level"

The "Sec10. Power-Saving Features" document for PIC24F, in subsection 3 "Instruction-Based Power-Saving Modes", the language is confusing, to me.   In section 10.3.1.6 "WAKE-UP FROM SLEEP ON INTERRUPT", talks about interrupts as assigned to a "CPU priority level".  But, there is also a CPU priority level, set by the IPL bits [4 in all], which, certainly, is a different thing, than an interrupt priority level, like the Change Notification [CNIP], or the Timer2 Interrupt Priority [T2IP].
 
So...why does this document use the term "CPU priority", when it seems to be referring to an IPC style interrupt priority?!?

For instance: "User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep
mode"
OR
"To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater."
 
How can a regular interrupt have a CPU priority level?!?  Isn't it just a priority level, and isn't CPU priority a different thing?
 
post edited by ReverseEMF - 2019/09/08 07:04:00

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NKurzman
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Re: Confusing language in documentation re "CPU Priority Level" & "interrupt priority leve 2019/09/08 00:23:09 (permalink)
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The interrupts must have a higher level then the cpu priority level or they will not fire.
Setting the CPU to the highest level effectively disables all interrupts.
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NorthGuy
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Re: Confusing language in documentation re "CPU Priority Level" & "interrupt priority leve 2019/09/08 05:48:26 (permalink) ☄ Helpfulby ReverseEMF 2019/09/08 11:25:53
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BlindedByDaLight
How can a regular interrupt have a CPU priority level?!?



When an ISR is invoked, the CPU priority level becomes equal to the interrupt priority level. It then reverts back when ISR returns. This way lower-priority interrupts are automatically blocked while ISR executes.
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ReverseEMF
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Re: Confusing language in documentation re "CPU Priority Level" & "interrupt priority leve 2019/09/08 11:24:51 (permalink)
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Thank you for the replies.
 
I also found the following [suggested in the "Related Threads"], which went a long way towards answering my questions regarding interrupt priority: https://www.microchip.com/forums/m328564.aspx?tree=true
 
 

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aschen0866
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Re: Confusing language in documentation re "CPU Priority Level" & "interrupt priority leve 2019/09/08 11:45:19 (permalink)
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BlindedByDaLight
How can a regular interrupt have a CPU priority level?!? Isn't it just a priority level, and isn't CPU priority a different thing?


This picture is for a PIC32 but the idea is the same. The CPU's priority level (IPLx) is part of the CPU core design. Then you have an interrupt controller that is outside of the core, which controls interrupt vectors' priority via those IPCx settings. An ISR can only be fired up if the interrupt vector's priority is higher than the current CPU's IPL. In a PIC24, the only way to disable global interrupt including the priority 7 interrupt is to raise the CPU's IPL to 7.
 
In the Single-Vector mode, a CPU always jumps to the same address, whereas in the Multi-Vector mode, the CPU jumps to a specific address based up the vector number.
 
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Nikolay_Po
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Re: Confusing language in documentation re "CPU Priority Level" & "interrupt priority leve 2019/09/08 14:40:51 (permalink)
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"User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep
mode"
"To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater."
I believe the CPU word may be completely omitted from these sentences.
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