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EZBL, FRC + PLL and baud rates

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mmorais
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2019/09/06 08:48:36 (permalink)
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EZBL, FRC + PLL and baud rates

Hey guys,
 
I'm trying to implement a dual partition EZBL on a custom board which I want to clock the system at FCY = 4MHz instead of the 16MHz that are EZBL's default. I can get the system running at the correct speed and the NOW_* variables are correctly calculated, but I'm having trouble with the UART baud rates when it comes to uploading firmware to the bootloader.
 
I've looked at the datasheet and saw the baudrate formulas et al, but I can't understand why it's not working. EZBL uses FRC with PLL 4x and no postscaler by default (with FCY = 16MHz), and at those values I can get it to work. But if I adjust CLKDIV to divide by 4 to account for my desired FCY' = FCY/4 = 4MHz, which I have to do to maintain the NOW_* values accurate, shouldn't I just need to also divide the default baudrate (230400) by 4? According to the formulas on the datasheet, the error rate should be the same, at around 8%.
 
Clearly I'm missing something... Also please note that I'm new at this PIC stuff :P
Thanks in advance
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