EZBL dual partition system clock
I'm trying to integrate EZBL dual partition on an existing firmware for the PIC24FJ256GA606. I've successfully integrated the single partition EZBL with the same firmware, and doing UART uploads works as expected (mostly, there's sometimes communication errors, but it's rare). The reason to go for the dual partition bootloader is to eventually implement OTA updates while the application is running and using the older partition as a failsafe.
So far, I've managed to adapt the dual partition bootloader to my board and have built a PoC firmware to flash 2 LEDs depending on the active partition, and it works great. Firmware UART uploads work fine as well, and I can change active partitions with a button. The problem is, I need to change FCY to a lower value, as the firmware I'm trying to integrate is optimized for low power consumption and uses a 4MHz FCY instead of EZBL's 16MHz default. As such, I attempted to reduce EZBL's FCY to 4MHz and set CLKDIV<7:6> bits (CPDIV bits) to 0x2 instead of the default 0x0 in order to get the PLL postscalar to also divide by 4. This works fine for setting the system clock and have the NOW_* variables adjusted accordingly.
However, this messes up the UART file uploads completely, and I cannot understand why (also please not that I'm no expert when it comes to serial communication, frequencies and baudrates xD). I'm using the same UART (in my case UART2) for both bootloader uploads and to send out status messages to the PC. These messages work fine if I adjust the baudrate from the default 230400 to 57600, which unsurprisingly is the former divided by 4. But no matter what baudrate I pick, I simply can't get file uploads to work; sometimes they timeout without any communication, sometimes they communicate for a while but end up returning an error at some point. (I'm using the provided ezbl_comm.exe to send files to my board.)
Now, it's worth mentioning that my original firmware doesn't use PLL at all and I've managed to get single partition EZBL running without PLL at the 4MHz frequency without doing anything special. But for the dual partition case, I can't seem to get it to work without using PLL. I've read that it is required if I'm using the USB module because it needs PLL/2 = 48MHz frequency, and for that matter also that FCY cannot be lower than 16MHz because of it, but I'm not using any USB modes. I'm just using UART2 connected to as a FT232 USB port. I'm not sure if this is in the way of making it work. In fact just out of curiosity, I've tried setting FCY = 8MHz and using CPDIV as a divide-by-2, and the result is that I can do firmware uploads about 50% of the time, but just when the first partition is active. This got me seriously confused xD.
Do you guys have any idea what might be going on? Any pointers you can give would be greatly appreciated!
Thanks in advance