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Hot!K42 Open Drain Question

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mpgmike
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2019/08/23 07:24:00 (permalink)
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K42 Open Drain Question

I am developing a project where I need to switch some P-MOSFETs at higher-than-Vdd voltages -- like upwards of 30 volts.  I scoured the data sheet Electrical Specifications section trying to find out how much voltage the pins can handle in Open Drain mode without success.  It just specifies 20 mA of current is the safety zone.  I intend to use a 10k pull-up resistor from the MOSFET Gate to Source then a 20k from PIC to Gate.  I do know if I breadboard it and it works, that's no guarantee it won't fail miserably in the field.  I'm hoping for someone from Microchip that can offer guidance, but welcome any experience anyone may have on this subject.

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#1

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    mbrowning
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    Re: K42 Open Drain Question 2019/08/23 08:02:42 (permalink)
    +1 (1)
    Datasheet clearly specifies absolute max on IO pins Vdd+0.3V. Mode of operation does not matter.

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    #2
    crosland
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    Re: K42 Open Drain Question 2019/08/23 08:31:13 (permalink)
    +1 (1)
    If in doubt, use a transistor or a proper MOSFET driver.
    #3
    Mysil
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    Re: K42 Open Drain Question 2019/08/23 08:43:55 (permalink)
    +1 (1)
    Hi,
    Nothing higher than the device power supply voltage:   Vdd + 0.3 Volt is allowed. 
    Even if the Output Pin driver stage may be configured for Open Drain use,
    the highside transistor of the output buffer is still there in the chip, and will act as a protection diode against voltage higher than power supply voltage. 
    The only effect of Open Drain control register, is that gate drive to the highside transistor is disabled.
     
    Whether protection diode is a parasitic effect of the highside transistor, or a separate structure, do not matter,
    if voltage higher than actual power supply is applied to an output pin, current will be conducted into the chip, and from there to the power supply pin. 
    Vdd + 0.3 Volt, is maximum allowed before noticable current will start leaking into the chip.
    Datasheet have specification of maximum current in protection diode, Clamp current Ik = 20 mA,
    but any current injected this way may have strange side effects, and is better avoided in normal operation.
     
    For driving a high-side mosfet at voltage higher than Vdd, a separate n-channel discrete transistor is sometimes used as voltage translator, or separate mosfet driver devices may be used.
     
    This is a user forum, and anything I write is Not Microchip guidiance.
     
        Mysil
     
    #4
    mpgmike
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    Re: K42 Open Drain Question 2019/08/23 09:52:46 (permalink)
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    From the PIC18(L)F26/27/45/46/47/55/56/57K42 data sheet (DS40001919B-page 341):

    23.1.2 OPEN-DRAIN OUTPUT OPTION
    When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters.

    This is why I assumed it could be done.  I just don't know how high a "higher level" is.

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    #5
    mbrowning
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    Re: K42 Open Drain Question 2019/08/23 10:15:59 (permalink)
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    Maybe read a little further:
    This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters.
     
    Note: The voltage on the pin should not exceed the maximum recommended voltage level for that pin

    Max recommended is not explicitly specified, but is implicitly specified as Vdd based on absolute max of Vdd+0.3
    The reason why is clear upon viewing Figure 16.1

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    Jerry Messina
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    Re: K42 Open Drain Question 2019/08/23 10:38:05 (permalink)
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    So that begs the question...
     
    If the max voltage is tied to the VDD spec then how does
    This feature allows the voltage level on the pin to be pulled to a higher level
    make any sense at all?
     
    #7
    mpgmike
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    Re: K42 Open Drain Question 2019/08/23 10:55:55 (permalink)
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    THUS THE CONFUSION!!  In the past I've used MOSFETs (2N7000, ULN2004, etc) to activate P-MOSFETS at higher voltages.  I thought I could get away with reduced hardware on this project.  However, the data sheet does offer ambiguity on the subject.  Perhaps I should just go the safe route.  BUT, if I could reduce hardware.....

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    #8
    Jerry Messina
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    Re: K42 Open Drain Question 2019/08/23 11:34:52 (permalink)
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    As mbrowning pointed out in #6, as long as the IO pin has protection diodes to VDD/VSS then that's pretty much going to be the limit.
     
    Hopefully that note isn't suggesting that you tie the pin to a higher voltage and just limit the current like in some of the past app notes.
    #9
    mpgmike
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    Re: K42 Open Drain Question 2019/08/23 15:53:32 (permalink)
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    I decided it would be worth sacrificing a PIC18F26K42 for the cause.
     
    Hardware:
    - PIC18F26K42
    - TP2104 P-MOSFET (40 volts, 175 mA rating)
    - 10k pull-up resistor between MOSFET Gate & Source
    - 22k resistor between PIC RA0 & Gate
    - 10k current limiting resistor between Drain & green LED (cathode tied to system ground)
     
    Software:
    - TRISA.0 = 0
    - ANSELA.0 = 0
    - OSCONA.0 = 1
     
    Algorithm:
    - LATA.0 = 1
    - Delay 200 ms
    - LATA.0 = 0
    - Delay 200 ms
     
    I connected a separate adjustable power supply to the Source on the MOSFET.  I started out with it at 0 volts.  Sure enough, the output from RA0 was nothing.  As I increased the voltage, the wave form from RA0 followed the power supply...up to about 5 volts.  I increased the supply voltage to about 30 volts; the LED just stayed on (no blinking), but the square wave at RA0 never went above around 5 volts.
     
    This answers my question: I must use a switch between the PORT.PIN and my P-MOSFET Gate.
    (ps, No PIC processors were harmed in this testing.)

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    #10
    NorthGuy
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    Re: K42 Open Drain Question 2019/08/23 16:12:31 (permalink)
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    To switch the FET off, you must take the gate close to the source. You have a voltage divide between 5V and 30V, so the gate is still at about 22V (as opposed to roughly 20V when PIC is at 0V). You need to tweak the resistors so that the gate gets through Vgth while PIC moves between 0 and 5V. I'm not sure you can get enough voltage amplitude on the gate to accomplish reliable switching.
     
    At any rate, with big resistors, FET will switch very slow.
    #11
    mpgmike
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    Re: K42 Open Drain Question 2019/08/23 17:48:27 (permalink)
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    I'm going to use a ULN2003 Darling Array for the switching & switch to a 1k resistor between the Darling and MOSFET.  The gate on my chosen part handles <40 volts between G-S.

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    #12
    crosland
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    Re: K42 Open Drain Question 2019/08/24 04:51:41 (permalink)
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    You
    Jerry Messina
    As mbrowning pointed out in #6, as long as the IO pin has protection diodes to VDD/VSS then that's pretty much going to be the limit.
     
    Hopefully that note isn't suggesting that you tie the pin to a higher voltage and just limit the current like in some of the past app notes.



    You can safely tie to a higher voltage through a resistor so long as the current is limited to be within the max for the protection diodes. It's done on many commercial products and I have done it myself.
    #13
    ric
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    Re: K42 Open Drain Question 2019/08/24 04:53:11 (permalink)
    +1 (1)
    However making those protection diodes conduct has been known to disturb ADC operation in some PICs.
     

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    #14
    Jerry Messina
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    Re: K42 Open Drain Question 2019/08/24 09:34:01 (permalink)
    +2 (2)
    They're not real keen on doing that anymore... it's worth taking a look at TB3009 and TB3013
     
    TB3009
    Note: Passing current through the ESD protection diodes of the device is outside of the
    operating conditions of the device causing potentially shortened device life span and
    incorrect functionality

    TB3013
    ... and the probability increases for unexpected behaviors when the data sheet
    specifications are violated


    In addition to ADC issues it can also cause problems with the osc circuit.
     
    You are, of course, free to do as you see fit.
    #15
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