• AVR Freaks

ADC sampling time problem with pic 24fj1024GB610 Help !

Author
hichamrol
Starting Member
  • Total Posts : 50
  • Reward points : 0
  • Joined: 2019/07/10 07:22:53
  • Location: 0
  • Status: offline
2019/08/23 02:21:13 (permalink)
0

ADC sampling time problem with pic 24fj1024GB610 Help !

Hi , 
i am using the ADC of my pic24fj1024GB610 , and i am reading a sinus signal 10Hz -> 100ms 
the problem is : i set my adc to give me about 1 sample every 0.123 ms,  that mean i will get 813 pts for one periode of my signal sinus 10 Hz. 
when i trace the graph of total pts calculated  i find that the period of the signal is about 45 ms and the the numbers of pts between two MAX is about 344 pts not even close to 813 pts , so i am confused and i think i missed something important , i dont know where is exactly the problem , 
for the configuration of my Adc , i am using auto sampling , and 16.TAD for the conversion, and for the clock source , i am using the internal FRC 8MHz Nominal ,  Doze mode is disabled , so Tcy is 250ns ... "" i generated the Clock init by MCC "
here the configuration .. thank you i will appreciate your help guys
// FSEC
#pragma config BWRP = OFF //Boot Segment Write-Protect bit->Boot Segment may be written
#pragma config BSS = DISABLED //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
#pragma config BSEN = OFF //Boot Segment Control bit->No Boot Segment
#pragma config GWRP = OFF //General Segment Write-Protect bit->General Segment may be written
#pragma config GSS = DISABLED //General Segment Code-Protect Level bits->No Protection (other than GWRP)
#pragma config CWRP = OFF //Configuration Segment Write-Protect bit->Configuration Segment may be written
#pragma config CSS = DISABLED //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
#pragma config AIVTDIS = OFF //Alternate Interrupt Vector Table bit->Disabled AIVT

// FBSLIM
#pragma config BSLIM = 8191 //Boot Segment Flash Page Address Limit bits->8191

// FOSCSEL
#pragma config FNOSC = FRC //Oscillator Source Selection->Internal Fast RC (FRC)
#pragma config PLLMODE = DISABLED //PLL Mode Selection->No PLL used; PLLEN bit is not available
#pragma config IESO = OFF //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source

// FOSC
#pragma config POSCMD = NONE //Primary Oscillator Mode Select bits->Primary Oscillator disabled
#pragma config OSCIOFCN = OFF //OSC2 Pin Function bit->OSC2 is clock output
#pragma config SOSCSEL = OFF //SOSC Power Selection Configuration bits->Digital (SCLKI) mode
#pragma config PLLSS = PLL_PRI //PLL Secondary Selection Configuration bit->PLL is fed by the Primary oscillator
#pragma config IOL1WAY = ON //Peripheral pin select configuration bit->Allow only one reconfiguration
#pragma config FCKSM = CSDCMD //Clock Switching Mode bits->Both Clock switching and Fail-safe Clock Monitor are disabled

// FWDT
#pragma config WDTPS = PS512 //Watchdog Timer Postscaler bits->1:512
#pragma config FWPSA = PR128 //Watchdog Timer Prescaler bit->1:128
#pragma config FWDTEN = OFF //Watchdog Timer Enable bits->WDT and SWDTEN disabled
#pragma config WINDIS = OFF //Watchdog Timer Window Enable bit->Watchdog Timer in Non-Window mode
#pragma config WDTWIN = WIN25 //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
#pragma config WDTCMX = WDTCLK //WDT MUX Source Select bits->WDT clock source is determined by the WDTCLK Configuration bits
#pragma config WDTCLK = LPRC //WDT Clock Source Select bits->WDT uses LPRC

// FPOR
#pragma config BOREN = ON //Brown Out Enable bit->Brown Out Enable Bit
#pragma config LPCFG = OFF //Low power regulator control->No Retention Sleep
#pragma config DNVPEN = ENABLE //Downside Voltage Protection Enable bit->Downside protection enabled using ZPBOR when BOR is inactive

// FICD
#pragma config ICS = PGD1 //ICD Communication Channel Select bits->Communicate on PGEC1 and PGED1
#pragma config JTAGEN = OFF //JTAG Enable bit->JTAG is disabled
#pragma config BTSWP = OFF //BOOTSWP Disable->BOOTSWP instruction disabled

// FDEVOPT1
#pragma config ALTCMPI = DISABLE //Alternate Comparator Input Enable bit->C1INC, C2INC, and C3INC are on their standard pin locations
#pragma config TMPRPIN = OFF //Tamper Pin Enable bit->TMPRN pin function is disabled
#pragma config SOSCHP = ON //SOSC High Power Enable bit (valid only when SOSCSEL = 1->Enable SOSC high power mode (default)
#pragma config ALTVREF = ALTREFEN //Alternate Voltage Reference Location Enable bit->VREF+ and CVREF+ on RA10, VREF- and CVREF- on RA9

// FBOOT
#pragma config BTMODE = SINGLE //Boot Mode Configuration bits->Device is in Single Boot (legacy) mode

 
void CLOCK_Initialize(void)
{
    // CPDIV 1:1; PLLEN disabled; DOZE 1:8; RCDIV FRC; DOZEN disabled; ROI disabled;
    CLKDIV = 0x3000;
    // STOR disabled; STORPOL Interrupt when STOR is 1; STSIDL disabled; STLPOL Interrupt when STLOCK is 1; STLOCK disabled; STSRC SOSC; STEN disabled; TUN Center frequency;
    OSCTUN = 0x00;
    // ROEN disabled; ROSWEN disabled; ROSEL FOSC; ROOUT disabled; ROSIDL disabled; ROSLP disabled;
    REFOCONL = 0x00;
    // RODIV 0;
    REFOCONH = 0x00;
    // DCOTUN 0;
    DCOTUN = 0x00;
    // DCOFSEL 8; DCOEN disabled;
    DCOCON = 0x700;
    // DIV 0;
    OSCDIV = 0x00;
    // TRIM 0;
    OSCFDIV = 0x00;
    // AD1MD enabled; T3MD enabled; T4MD enabled; T1MD enabled; U2MD enabled; T2MD enabled; U1MD enabled; SPI2MD enabled; SPI1MD enabled; T5MD enabled; I2C1MD enabled;
    PMD1 = 0x00;
    // OC5MD enabled; OC6MD enabled; OC7MD enabled; OC8MD enabled; OC1MD enabled; IC2MD enabled; OC2MD enabled; IC1MD enabled; OC3MD enabled; OC4MD enabled; IC6MD enabled; IC7MD enabled; IC5MD enabled; IC8MD enabled; IC4MD enabled; IC3MD enabled;
    PMD2 = 0x00;
    // I2C3MD enabled; PMPMD enabled; U3MD enabled; RTCCMD enabled; CMPMD enabled; CRCMD enabled; I2C2MD enabled;
    PMD3 = 0x00;
    // U4MD enabled; USB1MD enabled; CTMUMD enabled; REFOMD enabled; LVDMD enabled;
    PMD4 = 0x00;
    // IC9MD enabled; OC9MD enabled;
    PMD5 = 0x00;
    // SPI3MD enabled;
    PMD6 = 0x00;
    // DMA1MD enabled; DMA0MD enabled;
    PMD7 = 0x00;
    // U5MD enabled; CLC3MD enabled; CLC4MD enabled; CLC1MD enabled; CLC2MD enabled; U6MD enabled;
    PMD8 = 0x00;
    // CF no clock failure; NOSC FRC; SOSCEN disabled; POSCEN disabled; CLKLOCK unlocked; OSWEN Switch is Complete; IOLOCK not-active;
    __builtin_write_OSCCONH((uint8_t) (0x00));
    __builtin_write_OSCCONL((uint8_t) (0x00));
}

int main(void)
{
    // initialize the device
    SYSTEM_Initialize();
    UART1_Initialize();
    BUTTON_Enable(BUTTON_S3);
    
    ANSBbits.ANSB3 = 1; // pin 22 for
    AD1CHS = 3; // pin for gbf
    AD1CSSL = 0;
    AD1CON1 = 0x8470; // ADC ON /Mode 12 bits //Data form DSR // SSRC auto convert Mode
                      // ASAM=Sampling begins when SAMP bit is manually set
     
    AD1CON3 = 0x811c; //ADRC=4MHz Nominal //SAMC=Sample time = 1Tad / ADCS=29Tcy=TAD
    AD1CON2 = 0;
    //AD1CHS = 5; // selection channel 5 pour la conversion POT
   
    
    int i;
    uint16_t tab[8000];

    while(1)
    {
        if( BUTTON_IsPressed(BUTTON_S3)) //
        {
            AD1CON1bits.SAMP = 1; // Sample time = 1Tad // Tad = 29Tcy
            for(i=0;i<8000;i++)
               {
                 while (!AD1CON1bits.DONE);
                 tab[i] = ADC1BUF0;
                 AD1CON1bits.SAMP = 1;
               }
}
}
return 0;
}

 
 
 
#1

0 Replies Related Threads

    Jump to:
    © 2019 APG vNext Commercial Version 4.5