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RonGer
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2019/08/21 10:59:37 (permalink)
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Dspic33ev256gm104

Hello all,

I would like to implement a cyclic check of the flash memory, to my project. The problem is I have no idea where to start and what to consider. For this reason I wanted to ask whether someone has experience or maybe some code that he/she can share.

Thanks in advance and kind regards

Ron
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    JPortici
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    Re: Dspic33ev256gm104 2019/08/21 11:20:43 (permalink)
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    have you checked the class-b safety libraries? you will find a reference in the product page, document section
    #2
    du00000001
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    Re: Dspic33ev256gm104 2019/08/21 12:02:00 (permalink)
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    Find AN1778 and the associated lib!
    (The "Class B Safety Software Library ..." already mentioned above.)

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #3
    RonGer
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    Re: Dspic33ev256gm104 2019/08/22 00:18:16 (permalink)
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    Hello I already minded this library, but where can I download it and is it free? I thought it would be a commercial product.
    #4
    JPortici
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    Re: Dspic33ev256gm104 2019/08/22 00:35:38 (permalink)
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    If you follow the link to the app note you can download the documentation and the sources. In the documentation there should be the license, but i think it's free for commercial use, if used with microchip parts. (If you want to be sure contact support and/or your local FAE)
     
    Otherwise, in the documentation the principle is explained, you can always implement yourself but if you need pre-certified libraries.. contact support :)
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    RonGer
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    Re: Dspic33ev256gm104 2019/08/22 00:38:32 (permalink)
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    Okay thank you very much.
     
    By the way, maybe you can answer me this question as well, although it is a different topic.
    Does the DSPIC33EV256GM104 really has no EEPROM?
    I couldn't find it in the Datasheet. :(
    #6
    JPortici
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    Re: Dspic33ev256gm104 2019/08/22 00:49:15 (permalink)
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    If it ain't in the datasheet it ain't in the chip :(
    I wish microchip released a new EV series with more pins, dual partition flash and CAN-FD. I really dig the 5V (which is why we used them for so long) but having to deal with external eeproms for large amount of data it's a real PITA.
     
     
     
    In the meantime, most of the new projects in which 3V is not a big hassle are being done with the 33CK which has dual partition flash (and many more advanced features).
    Using the inactive partition has many advantages:
    -Being internal, it will be read protected, one can't read the data by sniffing the SPI/I2C bus
    -Being internal, in can be preloaded at programming time
    -Being internal, memory access takes way less time
    -No Negligible risk of corrupted data due to issue during read/write
    -In my case, the flash has enough erase/write cycles so i don't have to deal with an EEPROM emulation library
    -The inactive partition can be erased/written without stalling the CPU, so no loss of interrupts
     
    To be honest, i'd really like a 33CK working at 5V as an upgrade to the 33EV series :D i will happily accept a loss in performance if i can get one, to upgrade legacy boards
    #7
    RonGer
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    Re: Dspic33ev256gm104 2019/08/22 02:37:56 (permalink)
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    Okay many thanks for the verification :). I just wasn't sure whether my interpretation was right (would have assumed that such a kind of chip has no persistent memory).
     
    I red that the DSPIC33EV256GM104 flash memory has a cell endurance of 10000 E/W cycles.
    So from this side the flash memory loss wouldn't be such an big issue (At 256Kb Flash memory size with 21.8kB flash available for user program), for a EEPROM emulation.
     
    The bigger issue would be the CPU stall. For writing a a flash row of 192byte requires 0.691ms. Using to persistent memory copies in the flash, would lead to a CPU stall time of 1.382ms for a write access on the flash.
     
    Do you think/have experience with CAN/CAN FD/LIN buses and such a long blocking time. I think for LIN it shouldn't be an issue. But have no experience with CAN and CAN FD.
     
    Kind Regards

    Ron
     
     
    #8
    JPortici
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    Re: Dspic33ev256gm104 2019/08/22 03:24:45 (permalink)
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    Hm.. I haven't personally tested it because i needed to react to input captures/output compares occuring at a 100-500us rate so i couldn't rely on FIFOs, neither i could rely on DMA because 4 channels are too little :(
     
    However, canbus operates completely on its own and DMA must be used for canbus in the dsPIC33EV, so maybe you could increase the depth of your FIFOs in order to prevent read overflow and write underflow..
     
    I don't know, you should test it. (and you can use the dsPIC33EV can/lin starter kit to test in case. Reasonably cheap and you will get better support as the support staff can use their own hardware to test in caseyou have any issue)
     
    Another thing about CAN + DMA... DMA will be triggered very frequenctly to do realtively long transferts, so if i were you i would use channel 2 and 3 (lowest priority), otherwise if you used dma for something like, say, ADC+SCAN to automatically scan a number of ADC channels you would lose samples (and worse syncronism, acquire channel 3 but result goes in channel 6 buffer) because the ADC DMA request will wait for the CAN DMA transfert to end
    #9
    RonGer
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    Re: Dspic33ev256gm104 2019/08/22 04:54:13 (permalink)
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    Hello JPortici,
     
    thank you for the very valueable information. Because of this I already have the next question. I hope I don't ask to many questions
    I calculated that on erase/write cycle will take ~21ms (Erase 1536byte page and write one 192byte word).
    When I assume a CAN bus with 500kbit/s, I would have to cover 0.021s/0.000016s = 1312byte with the DMA, while the CPU is in stall.
    The SRAM of the DSPIC is 16kB, which should be big enough. The question is, do you see any problems with storing that many data over DMA to SRAM?
     
    Further I have to perform a ADC sampling sequence, which also uses DMA. (I'm currently investigating the gaps between DMA occupation and the entire duration of the sequence.). Both would be in competiton about the DMA ressource. I red in the data sheet that the DSPIC33EV has 32 receive buffers (with 8byte depths). I have further red that these message buffers are located in the SRAM. To access this SRAM I assume the DMA is necessary.
    For this reason I'm asking myself how many byte can the CAN module buffer? The CAN Reveive register seems to have only 16bit depth. So is my understanding correct that the CAN RX Buffer is useless when the DMA is blocked by another macro?
     
    #10
    JPortici
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    Re: Dspic33ev256gm104 2019/08/22 05:07:08 (permalink)
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    For the RAM, no right now i don't see a problem in storing 1k of data with DMA. too many unknowns to tell for sure.
    You could also ask yourself if not using an eeprom is mandatory, if 5V I/O are really that important otherwise i'd suggest you to use another strategy (like moving to a different family which will let you use the secondary flash panel as storage medium without stalling the cpu)
    Or on how frequently you have to write and then erase the memory (it could be done only in particular moments, when canbus is inactive for example... All questions you and only you can answer for yourself.
     
    Naturally, your numbers are a bit exaggerated. Even if you are logging every possible frame in a bus that is 100% loaded you'd still have less bytes to store due to bit stuffing and interframe periods and the fact that some of the information like CRC is not transferred to memory
     
    for the ADC, just refer to the reference manual (the ADC chapter linked in the dsPIC product page. Always refer to the one in the specific product page, as there are several ADC cores in the dsPIC line, the one you have to use is the one listed in the product page.)
    In there you will find an example of ADC+DMA in scatter/gather mode. This mode lets you use the Channel scan feature with DMA.
    As i said before, assign the highest priority DMA channel for the ADC (DMA0) otherwise if it can't process the transfert before the next acquisition, the current acquisition will be lost and it will break the acquisition until you reset both peripherals.
     
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    RonGer
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    Re: Dspic33ev256gm104 2019/08/22 06:35:28 (permalink)
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    Okay understood.
    One last question: Can I assume a maximum blockage time for the DMA in the nanosecond range (as for RAM), for a 2 byte write to RAM (CAN Receive buffer depth: 2byte/ ADC sample buffer: 2byte).
    I would like to understand which maximum delay for writting I have to expect.
    When you have a more accurate number, I would be highly interested to know it.
     
    (background: At 500kbits for CAN communication I expect each 16µs a new byte. After 32µs the CAN receive register is full. So the data need to be transfered from this time on. So I would like to know how long the DMA is blocked by the CAN or the ADC (bit 2byte to transfer each time).)
     
    Thanks in advance and kind regards
     
    Ron
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    JPortici
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    Re: Dspic33ev256gm104 2019/08/23 00:16:42 (permalink)
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    This is an interesting question.
    I would assume that the transfert speed is one word (two bytes) per clock cycle or per Tcy (so two clock cycles)
    but this is outside my knowledge and what i cared to verify.
    You could set up a sample program with something like this..
    -set up a timer with 1:1 clock prescaler
    -set up dma, enable interrupt at transfert complete
     
    -clear timer
    -enable timer
    -software trigger of dma
     
    -while(1) empty loop
     
    at the transfert complete interrupt, stop the timer and read the value, if should give you an idea
    #13
    RonGer
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    Re: Dspic33ev256gm104 2019/08/29 01:58:14 (permalink)
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    Hello JPortici,
     
    in the meantime I developed a concept, which I try to describe in the following lines.
     
    1. Four data structure in flash. Two data structures are pair, which contains redundant copies of the persistent data.
     
    2. One of the structure pairs is the active pair the other one is the unused, which is in erased state and can be written at all times.
     
    3. At boot the SW checks which structure pair is the active one and which is the unused or inactive one.
     
    4. In case that there is a inactive structure the structure gets erased and becomes unused at the SW boot.
     
    5. SW will copy the content of the active structure into the RAM.
     
    6. A active structure can be identified by a marking in the first line of the reserved memory of this structure.
     
    7. A inactive structure can be identified by the active marking in the first line and a inactive marking in the second line of the reserved memory structure.
     
    8. In the third line a counter will be included, which counts the erase/write cycles for this structure. As a part of the erase procedure the counter value will be written.
     
    During SW/Application runtime only writting will be feasible.
     
    With this I achieve a virtual flash endurance for the SW of 20000 write/erase cycles.
    Overall this seems to be very complicated to me. For this reason I would like to ask you for your concept.
    Is it that complex as mine or do you have an simpler/smarter or even more complex concept?
    And in general with your experience of emulating EEPROM on the device, what is your opinion about the concept?
     
    Kind Regards
     
    Ron
     
     
     
     
    #14
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