Re: ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision
So, I don't use this device, but I do depend on precise timing and use other 32 bit processors. So I will give you my opinion (FWIW).
The internal clock trees aren't typically characterized because the internal clock(s) were not meant to drive other devices. The clock tree only has to provide low enough jitter to run all the internal peripherals (We all assume that they did that right). The internal PLL is very wide range and of very low Q - Expect to see jitter if you put it on a phase noise system. See the ADC section of the DS for a discussion of ADC sampling jitter, this is usually where the jitter effects show up first - in degraded ADC SNR.
As to your question - it sounds like you want to phase lock and divide your oscillator down to some other frequency? By using a timer interrupt? If so, then this will incur a 'huge' increase in possible jitter. Now you have crossed the hardware domain and will have to deal with software interrupt latency - How many clock slips, typically? What if other interrupts are running too? they have to finish first. All these are real sources of jitter. Then there is the peripheral bus synchronization to toggle a pin (If that's what you are going to do) - more possible jitter, and it is a lot because it is whole, probably multiple clock slips, not just a little jitter on a stable clock.
With your stated need for highest performance, IMHO I think you need an external clock tree driver that meets your system jitter requirements and then drive the processor as a node from that.
Hope this helps, probably not, but anyway......