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Hot!ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision

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trey_german
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2019/08/08 07:34:03 (permalink)
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ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision

MC Experts,
First, could I suggest you make forums for the Atmel products you've acquired?  I was told on twitter to post my question for the ATSAMV71Q21 here because the proper forum doesn't exist.
 
We'd like to use this device to act as a PTP grand master (among other things).  I've got a sub 1 ppb tcxo driving the XIN of the device now.  Since the PLL seems to be uncharacterized, is the best way to maintain the accuracy of this txco internal to the device to run a timer off PCK6/7 and then derive that from MAINCK?
 
It would really be helpful to have a full clock tree diagram of this device.  Cross referencing through the datasheet to try to cobble together an understanding of the full clock tree sucks and is prone to error.  You really need to work on your documentation.
Thanks,
Trey
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    trey_german
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    Re: ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision 2019/08/12 11:00:48 (permalink)
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    Bump... 
    Any MC apps engineers help would be appreciated.  TI at the very least responds within 24 hours....
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    Jim Nickerson
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    Re: ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision 2019/08/12 11:12:46 (permalink)
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    You might be so bold as to open a support ticket to ask Microchip directly, this is a peer forum that some Microchip engineers occasionally watch.
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    LostInSpace
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    Re: ATSAMV71Q21 PLL Characterization/Timing Accuracy/Precision 2019/08/12 19:45:08 (permalink)
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    So, I don't use this device, but I do depend on precise timing and use other 32 bit processors. So I will give you my opinion (FWIW).
     
    The internal clock trees aren't typically characterized because the internal clock(s) were not meant to drive other devices. The clock tree only has to provide low enough jitter to run all the internal peripherals (We all assume that they did that right). The internal PLL is very wide range and of very low Q - Expect to see jitter if you put it on a phase noise system. See the ADC section of the DS for a discussion of ADC sampling jitter, this is usually where the jitter effects show up first - in degraded ADC SNR.
     
    As to your question - it sounds like you want to phase lock and divide your oscillator down to some other frequency? By using a timer interrupt? If so, then this will incur a 'huge' increase in possible jitter. Now you have crossed the hardware domain and will have to deal with software interrupt latency - How many clock slips, typically? What if other interrupts are running too? they have to finish first. All these are real sources of jitter. Then there is the peripheral bus synchronization to toggle a pin (If that's what you are going to do) - more possible jitter, and it is a lot because it is whole, probably multiple clock slips, not just a little jitter on a stable clock.
     
    With your stated need for highest performance, IMHO I think you need an external clock tree driver that meets your system jitter requirements and then drive the processor as a node from that.
     
    Hope this helps, probably not, but anyway......
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