Re: dsPIC33CH512MP506 AUDIO CODEC SPI
The CODEC is configured as the master and supplies bit clock (BLCK) and left/right clock (LRC) to the SPI module. Data is stereo arranged as two 16 bit channels. In DSP mode the SPI buffer full interrupt is continuously triggered every 32 clock cycles irrespective of the LRC state. In I2S mode I get a single interrupt on initialisation and then nothing, despite the CODEC sending the LRC framing signal, clock and data.