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Hot![SOLVED] - dsPIC33CH512MP506 AUDIO CODEC SPI

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rontaylor
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2019/08/03 09:19:49 (permalink)
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[SOLVED] - dsPIC33CH512MP506 AUDIO CODEC SPI

Hi,
 
I'm trying to get the slave core of the dsPIC33CH512MP506 to work with a stereo audio CODEC, a TLV320AIC23B. The simple bit banged control interface which is used to configure the CODEC works fine but getting the SPI module to communicate with the CODEC's digital audio interface mode has so far proved elusive. Has anyone had any success in using the SPI module in audio modes?
 
Regards
 
Ron
Penrith UK
post edited by rontaylor - 2019/08/08 09:06:18
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    du00000001
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    Re: dsPIC33CH512MP506 AUDIO CODEC SPI 2019/08/03 12:42:26 (permalink)
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    Issues with implementing I2S ?
    If I got it, have a look at  https://www.microchip.com/forums/m1105331.aspx

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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    rontaylor
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    Re: dsPIC33CH512MP506 AUDIO CODEC SPI 2019/08/04 05:06:25 (permalink)
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    Hi,
     
    The CODEC is configured as the master and supplies bit clock (BLCK) and left/right clock (LRC) to the SPI module. Data is stereo arranged as two 16 bit channels. In DSP mode the SPI buffer full interrupt is continuously triggered every 32 clock cycles irrespective of the LRC state. In I2S mode I get a single interrupt on initialisation and then nothing, despite the CODEC sending the LRC framing signal, clock and data.
     
    Very odd.
     
    Ron
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    du00000001
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    Re: dsPIC33CH512MP506 AUDIO CODEC SPI 2019/08/04 05:53:24 (permalink)
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    You're following CE117 or trying "your own thing"? (I didn't yet dig deeper into this topic.)
    From the above, your SPI is configured as a slave?
    Does it transmit on MOSI or is there only activity on MISO?

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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    rontaylor
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    Re: dsPIC33CH512MP506 AUDIO CODEC SPI 2019/08/04 08:45:06 (permalink)
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    I'm doing my own thing based upon DS70005136A and the TLV320AIC23B CODEC data sheet. I've had no problems getting this to work on single core dsPIC33EP processors using the DCI interface but the only option on this particular dual core processor is the SPI module "With Audio Support".
     
    I've ditched the audio protocol mode (AUDEN=0) and attempted to define the interface from the options in the SPI config registers. The processor's SPI module is a slave to the CODEC and receives data, LRC and clock. It sees those because it is generating "buffer full" interrupts. However, it does not currently produce transmit data back to the CODEC and the interrupts are at twice the sampling rate. I'm curious to know if anyone has managed to get audio protocol working on this SPI with common CODECs such as the TLV320AIC23B.
     
    Regards Ron
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    rontaylor
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    Re: dsPIC33CH512MP506 AUDIO CODEC SPI 2019/08/08 08:50:43 (permalink)
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    Hi All,
     
    I finally managed to get the CODEC audio SPI interface working although paradoxically not with the SPI in audio mode. (No matter what I tried I could not get the audio SPI to work in audio mode). I made a "ground up configuration" which makes the SPI module slave to a Texas TLV320AIC23B CODEC operating as master in DSP communications mode. The CODEC supplies clock and frame sync pulses to the SPI module with simultaneous Tx/Rx data transfer on the first rising clock edge following the frame sync leading edge. The CODEC clock is at 3.057MHz  taking a little over 10usec to make the data transfer, as this is a hardware implemented module, other than Tx/Rx data transfer, this will have no impact upon processor time. 
     
    For the benefit and mental health of others who make walk this path I attach below my SPI configuration code. Not shown here is the second, simple unidirectional bit banged SPI interface which is used to configure the CODEC and manage its functions during operation. The interface below is only for carrying 16bit stereo audio data between the CODEC and processor.
     
    Whilst perhaps not the last word in coding elegance it works...
     
    Regards
     
    Ron Taylor G4GXO
    Penrith UK

     
    // Eden dsP Dual Core
    //
    // (c)Ron Taylor G4GXO
    //
    // CODEC Audio SPI Interface
    //
    // Initialise CODEC SPI interface for PCM/DSP mode, Slave to CODEC
     
    void spi_init(void){   
     
    // SPI1 Configuration for PCM/DSP Communications in Slave Mode
    //
    // These settings configure the SPI module to communicate as a slave to the Texas
    // TLV320AIC23B stereo CODEC operating as a master device in DSP communications
    // mode (FOR1, FOR0 =1). Four signal lines are used;
    //
    //  CODEC           SPI
    //  DOUT    ---->   SDI
    //  LRCOUT  ---->   SS
    //  DIN     <----   SDO   
    //  BCLK    ---->   SCK (CODEC MCLK/4 = 3.057MHz for 12.228MHz Xtal)
    //   
        //  Clear Registers
        SPI1CON1L=0;                // Make sure all settings are cleared   
        SPI1CON1H=0;                // and module is disabled.  
        SPI1BUFL=0;                 // Clear Low Buffer
        SPI1BUFH=0;                 // Clear High Buffer
        SPI1IMSKL=0;                // Clear interrupt masks
        SPI1IMSKH=0;                //
     
        IEC0bits.SPI1RXIE=0;        // Disable interrupts
        IFS0bits.SPI1RXIF=0;        // Clear Interrupt flag
        IPC2bits.SPI1RXIP=4;        // Set interrupt priority
     
    /*  Configure Register SPI1CON1L
     *
     *  All Master mode and unused bits are set to zero
     *
     *  Bit  State   Name       Function
     *  15      0   SPIEN       Module disabled  
     *  14      0   Unimplemented 
     *  13      0   SPISIDL     Module continues operation in CPU idle state
     *  12      0   DISSDO      SDO controlled by module
     *  11      1   MODE        32 bit data length
     *  10      0   MODE        "       "       "      
     *  9       -   SMP         Rx data sampling mid bit (Master mode only)
     *  8       1   CKE         Transmit on clock high to low edge
     *  7       1   SSEN        SSx Pin in use
     *  6       0   CKP         Clock idle low, active high
     *  5       0   MSTEN       Slave mode
     *  4       0   DISSDI      SDI controlled by module   
     *  3       -   DISSCH      SCK controlled by module (Master mode only)
     *  2       -   MCLKEN      PBCLK used by BRG (Master mode only)
     *  1       0   SPIFE       Frame sync precedes first clock cycle
     *  0       1   ENHBUF      Enhanced buffer
     */  
        SPI1CON1L=0x0981;   // Load configuration low
       
    /*  Configure Register SPI1CON1H
     *
     *  All Master mode and unused bits are set to zero
     *
     *  Bit  State   Name       Function
     *  15      0   AUDEN       Audio mode disabled  
     *  14      0   SPISGNEXT   Data from FIFO is not sign extended 
     *  13      1   IGNROV      Rx Overflow (ROV) not critical   
     *  12      1   IGNTUR      Tx Underrun (TUR) not critical
     *  11      0   AUDMONO     Audio data is stereo
     *  10      0   URDTEN      Send the last received data during Tx Underrun  
     *  9       1   AUDMOD      PCM/DSP format
     *  8       1   AUDMOD      "          "
     *  7       1   FRMEN       Framed SPI, SSx is sync input
     *  6       1   FRMSYNC     Frame sync input   
     *  5       1   FRMPOL      Frame sync active high
     *  4       -   MSSEN       Master mode setting          
     *  3       0   FRMSYPW     Frame sync one clock cycle duration
     *  2       -   FRMCNT      Master mode settings
     *  1       -   FRMCNT      "       "       "
     *  0       -   FRMCNT      "       "       "
     */
        SPI1CON1H=0x33E0;           // Load configuration high
     
        SPI1STATLbits.SPIROV = 0;   // Clear Overflow flag   
        IFS0bits.SPI1RXIF=0;        // Clear Interrupt flag
        IPC2bits.SPI1RXIP=4;        // Set interrupt priority
        SPI1IMSKLbits.SPIRBFEN = 1; // SPI1 Rx Buffer full generates interrupt event
        IEC0bits.SPI1RXIE=1;        // Enable interrupts       
        SPI1CON1Lbits.SPIEN=1;      // Module enabled      
    }
     

      
    post edited by rontaylor - 2019/08/08 08:52:20
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