ICD 3 and dsPIC33EV256GM106 troobleshoot : The target device is not ready for debugging.
I am currently working on a project using a dsPIC33EV256GM106
. This Microchip is implemented on a custom board providing 5V between the Vdd/Avdd and Vss/Avss pins and a RJ45 wire connection for ICD 3
I had a lot of problem with this custom board (which in fact wasn't designed by myself) and I had to fix and change some settings to finally be able to program the device.
My problem is the following :
I am trying to debug my program on the device, using ICD 3 and MPLAB X on Linux (on PGEC1 and PGED1). But an error message is displayed
in the ICD 3 window (see ICD 3 verbose and error).
So, after a lot of research on manuals (Data sheet, RF, ICD 3 user's guide, ICD 3 design advisory) and some modifications made on the PCB for Avdd and Avss and Vcap, I still have this issue.
I have tried to set the internal oscillator (FRC), disable the watchdog, set the FICD register to PGD1, disable every code protection by using preprocessor configuration bits and also the _Macros. Still the problem persists (see Configuration code).
I am really confused by the fact that the device can be programmed
and can execute a simple blink Led code but can't be debugged
So I am asking myself those questions :
- Am I missing something on the device configuration bits ?
- Is there an alternative way to configure those bits (like using assembly language) (I have tried to check the memory but don't know how to interpret the .hex file)
- I have noticed a resistor of 470 ohm on both PGC and PGD wires. Can it induce problems for debugger ?
- No external oscillator is present on the board. Should I use one or is FRC good enough for debug ?
Thank you in advance for any suggestion you could provide me.
Xavier Complementary Information :
- ICD 3 is perfectly working with dsPIC30.
- the dsPIC33 can be programmed using ICD 3.
- the dsPIC33 is executing the blink program correctly.
- MBLAB version :
Product Version: MPLAB X IDE v5.20
Java: 1.8.0_181; Java HotSpot(TM) 64-Bit Server VM 25.181-b13
Runtime: Java(TM) SE Runtime Environment 1.8.0_181-b13
System: Linux version 4.15.0-54-generic running on amd64; UTF-8; fr_FR (mplab)
- IDC 3 to Microchip pins : CLK checked with a 10450 ohm pull-up resistor, Vdd ok, Vss ok, PGD and PGC with a 450 ohm resistor (?).
- Other information can be provided. ICD 3 verbose and error :
*****************************************************Macro configuration bits :
Connecting to MPLAB ICD 3...
Currently loaded firmware on ICD 3
Firmware Suite Version.....01.56.00
Target voltage detected
Target device dsPIC33EV256GM106 found.
Device Revision ID = 4006
The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x5ff
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.
_FSEC(BWRP_OFF & BSS_DISABLED & BSS2_OFF & GWRP_OFF & GSS_DISABLED & CWRP_OFF & CSS_DISABLED & AIVTDIS_DISABLE); //Disable table/code/program/whatever protect Or preprocessor Configuration bits :
_FOSCSEL(FNOSC_FRC & IESO_ON); //Fast oscillator selected
//_FOSC(OSCIOFNC_OFF); //Primary oscillator off
_FICD(ICS_PGD1); //Chossing PGEC1 and PGED1 for debugging
_FWDT(FWDTEN_OFF); //setting off the Watch dog timer
#pragma config BWRP = OFF // Boot Segment Write-Protect Bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSS2 = OFF // Boot Segment Control Bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect Bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect Bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = DISABLE // Alternate Interrupt Vector Table Disable Bit (Disable Alternate Vector Table)
#pragma config BSLIM = 0x1FFF // Boot Segment Code Flash Page Address Limit Bits (Enter Hexadecimal value)
#pragma config FNOSC = FRC // Initial oscillator Source Selection Bits (Internal Fast RC (FRC) Oscillator with divide by 16)
#pragma config IESO = OFF // Two Speed Oscillator Start-Up Bit (Start up device with FRC,then automatically switch to user selected oscillator source)
#pragma config POSCMD = NONE // Primary Oscillator Mode Select Bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin I/O Function Enable Bit (OSC2 is clock output)
#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration Bit (Allow Only One reconfiguration)
#pragma config FCKSM = CSDCMD // Clock Switching Mode Bits (Both Clock Switching and Fail-safe Clock Monitor are disabled)
#pragma config PLLKEN = ON // PLL Lock Enable Bit (Clock switch to PLL source will wait until the PLL lock signal is valid)
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler Bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler Bit (1:128)
#pragma config FWDTEN = OFF // Watchdog Timer Enable Bits (WDT and SWDTEN Disabled)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable Bit (Watchdog timer in Non-Window Mode)
#pragma config WDTWIN = WIN25 // Watchdog Window Select Bits (WDT Window is 25% of WDT period)
#pragma config BOREN0 = OFF // Brown Out Reset Detection Bit (BOR is Enabled)
#pragma config ICS = PGD1 // ICD Communication Channel Select Bits (Communicate on PGEC1 and PGED1)
#pragma config DMTIVTL = 0xFFFF // Lower 16 Bits of 32 Bit DMT Window Interval (Enter Hexadecimal value)
#pragma config DMTIVTH = 0xFFFF // Upper 16 Bits of 32 Bit DMT Window Interval (Enter Hexadecimal value)
#pragma config DMTCNTL = 0xFFFF // Lower 16 Bits of 32 Bit DMT Instruction Count Time-Out Value (Enter Hexadecimal value)
#pragma config DMTCNTH = 0xFFFF // Upper 16 Bits of 32 Bit DMT Instruction Count Time-Out Value (Enter Hexadecimal value)
#pragma config DMTEN = DISABLE // Dead Man Timer Enable Bit (Dead Man Timer is Disabled and can be enabled by software)
#pragma config PWMLOCK = OFF // PWM Lock Enable Bit (Certain PWM registers may only be written after key sequence)
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pins Selection Bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config CTXT1 = NONE // Interrupt Priority Level (IPL) Selection Bits For Alternate Working Register Set 1 (Not Assigned)
#pragma config CTXT2 = NONE // Interrupt Priority Level (IPL) Selection Bits For Alternate Working Register Set 2 (Not Assigned)