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Hot!PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT

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Joaquin
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2019/07/17 10:41:06 (permalink)
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PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT

PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT
 
I am actually setting up an application on MPASMX v5.83 based on the PIC18F46K42 microcontroller.
I will be using a large number of routines I programmed years ago on assembler. That way I am initially programming on MPASMXv.5.85 to check a concept.
Application use 2 push button switches and, Rotary encoder with push button and 2 sine wave input signals to be ZCD for a Phase Detector. . Action on those elements should start IRS.
Although I believe I am following the PIC18F46K42 Vectored Interrupts data sheet requirements, I have not been able to run properly even a simple IOC routine.
The INTERRUPTS .ARRANGEMENT.ASM source file is actually testing simple Vectored Interrupts IOC (RD4 & RD5),INT0(RB0),INT1(RA4)&INT2(RA5).CONFIG MVECEN = ON is setup (CONFIG2L) so the Vector table is used to determine the interrupt priorities.
That way:
;    INT0,RB0,p8 for Rotary Encoder Push Button(RE)
;    INT1,RA4,p23. & INT2,RA5,p24 for Push Button Switches
;    IOCC6: RC6, RE.B,p44 & IOCC7: RC7, RE.A,p1
; NOTES:
;               1) PERIPHERAL PIN SELECT (PPS) MODULE was contemplated for INT0, INT1 & INT2 setting 
;               2) CMP1 & CMP2 interrupts are not properly set up at this moment.
;               They will be used after analyzing Vectored Interrupt behavior for simple IOC and INT0, INT1 analysis.
 
The INT0, INT1 & INT2 based on Interrupt on falling edge of PPS selected pins for INTi reinitialize the code when applied.
Changing status on pins targeting IOCC6 & IOCC7 did nothing. It clearly loos like that I am not handling and setting up properly the INTERRUPT VECTOR TABLE (IVT).
 
I set up the IVTBASE registers default to 00 0008h, with the high priority interrupt vector address on 00 0008h and the low priority interrupt vector address will be 00 0018h.  
 
----------------;-----------------------------------------------------------------------------   
; INTERRUPTS: 00 0008h location is used as the reset default for the IVTBASE
; register, the vector table can be relocated in thememory by programming the IVTBASE register.
;The IVTBASE register is user programmable and is
; used to determine the start address of the Interrupt
; Vector Table and the IVTLOCK register is used to prevent any unintended writes to the IVTBASE register.
;;******************************************************************************
;-----------------------------------------------------------------------------             
    ; (IVTBASE = 0X08)
;Interrupt Vector Address ; Vector Number, Interrupt Source
    ORG   0x0008; 0 - Software Interrupt
    ORG   0x000A; 1 - HLVD
    ORG   0x000C; 2 - OSF
    ORG   0x000E; 3 - CSW
    ORG   0x0010; 4 - NVM
    ORG   0x0012; 5 - SCAN
    ORG   0x0014; 6 - CRC
    CODE 0x0016; 7 - IOC
                BRA                        ISR_IOC                                ; RE PINS A OR B PRESSED
    ORG   0x0018; 8 - INT0
                BRA                        ISR_INT0              ; PROCESS ISR INT0,ROTARY ENCODER PB, RB0
    ORG   0x001A; 9 - ZCD 51
    ORG   0x001C; 10 - AD
    ORG   0x001E; 11  ADT
    ORG   0x0020; 12 - C1
    bra                     ISR_CMP1                           ; VF ZCD
    ORG   0x0022; 13 - SMT1
    ORG   0x0024; 14 - SMT1PRA
    ORG   0x0026; 15 - SMT1PWA
    ORG   0x0028; 16 - DMA1SCNT
    ORG   0x002A; 17 - DMA1DCNT
    ORG   0x002C; 18 - DMA1OR
    ORG   0x002E; 19 - DMA1A
    ORG   0x0030; 20 - SPI1RX
    ORG   0x0032; 21 - SPI1TX
    ORG   0x0034; 22 - SPI1 64
    ORG   0x0036; 23 - I2C1RX
    ORG   0x0038; 24 - I2C1TX
    ORG   0x003A; 25 - I2C1
    ORG   0x003C; 26 - I2C1E
    ORG   0x003E; 27 - U1RX
    ORG   0x0040; 28 - U1TX
    ORG   0x0042; 29 - U1E 
    ORG   0x0044; 30 - U1 
    ORG   0x0046; 31 - TMR0
    ORG   0x0048; 32 - TMR1
    ORG   0x004A; 33 - TMR1G
    ORG   0x004C; 34 - TMR2
    ORG   0x004E; 35 - CCP1
    ORG   0x0050; 36 - ?
    ORG   0x0052; 37 NCO
    ORG   0x0054; 38 CWG1
    ORG   0x0056; 39 CLC1
    ORG   0x0058; 40 INT1
    BRA                        ISR_INT1                          ; PROCESS ISR INT2, PUSH BUTTON SWITCH SW.PB1
    ORG   0x005A; 41 C2   
    BRA                        ISR_CMP2                       ; Vz ZCD
    ORG   0x005C; 42 DMA2SCNT
    ORG   0x005E; 43 DMA2DCNT
    ORG   0x0060; 44 DMA2OR
    ORG   0x0062; 45 DMA2A
    ......................................
;-------------------------------------------------------------
 
Any hint?
 
Following NorthGuy considering Predetermined addresses evenly divisible by 4 and DS40001919E-page 133 , EXAMPLE 9-3: SETTING UP VECTORED INTERRUPTS USING MPASM, IVT worked as expected:
 
i.e
;-----------------------------------------------------------------------------    
    ; (IVTBASE = 0X08)
;Interrupt Vector Address ; Vector Number, Interrupt Source
    ORG    0x0008; 0 - Software Interrupt
    ORG    0x000A; 1 - HLVD
    ORG    0x000C; 2 - OSF
    ORG    0x000E; 3 - CSW
    ORG    0x0010; 4 - NVM
    ORG    0x0012; 5 - SCAN
    ORG    0x0014; 6 - CRC
    ORG    0x0016; 7 - IOC
    DW    ISR_IOC>>2        ; RE PINS A OR B PRESSED
    ORG    0x0018; 8 - INT0
    DW    ISR_INT0>>2        ; PROCESS ISR INT0, ROTARY ENCODER PB, RC7
    ORG    0x001A; 9 - ZCD 51
    ORG    0x001C; 10 - AD
    ORG    0x001E; 11  ADT
    ORG    0x0020; 12 - C1
    DW    ISR_CMP1>>2        ; VF ZCD
    ORG    0x0022; 13 - SMT1
post edited by Joaquinete33 - 2019/07/30 19:03:32
#1

8 Replies Related Threads

    Joaquin
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/18 14:39:51 (permalink)
    0
    The IVT I arranged should be valid since  CONFIG MVECEN = ON   ;(Multi-vector enabled, Vector table used for interrupts). Correct?
     
    Theoretically matches the TABLE - IVT OF PIC18FXXK42 FOR IVTBASE = 0008h.PDF Table. Is not it?
    #2
    NorthGuy
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/18 15:09:51 (permalink)
    +1 (1)
    The IVT table contains ISR addresses (as in PIC24). The interrupt controller doesn't jump to IVT, but rather fetches the ISR address from IVT.
    post edited by NorthGuy - 2019/07/18 15:10:52
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    Joaquin
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/18 20:39:43 (permalink)
    0
    Thank you NorthGuy.. Clear it is now..
     
    I completely misunderstood the IVT configuration..... I wrongly thought the ISR addressees were precisely the ones marked on DS40001919E Table 9-2 instead the PGM address  stored on them shifted twice.
    #4
    mpgmike
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/19 13:42:08 (permalink)
    0
    Here is a working example for a K42:

    Vector_Table_Init:
    MOVLW 0x00 ;Vector Table Start Address: 00 4008h
    MOVWF IVTBASEU, ACCESS
    MOVLW 0x40
    MOVWF IVTBASEH, ACCESS
    MOVLW 0x08
    MOVWF IVTBASEL, ACCESS
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Create Interrupt Vector Addrerss for DMA1SCNT_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;DMA1SCNT_INT = Vector #16
    MOVWF TBLPTRU, ACCESS ;4008h + [(16d) 10h * 2] = 4028
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x28
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link DMA1DCNT_INT ISR To Vector Address *** ---
    MOVLW 0x00 ;DMA1DCNTISR = 0x3000 >> 2 = 0C00h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= *** ---
    ; --- *** Create Interrupt Vector Address for U1RX_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;U1RX_INT = Vector #27
    MOVWF TBLPTRU, ACCESS ;4008h + [(27d) 1Bh * 2] = 0x403E
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x3E
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link U1RX_INT ISR To Vector Address *** ---
    MOVLW 0x08 ;U1RXISR = 0x3020 >> 2 = 0C08h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= *** ---
    ; --- *** Create Interrupt Vector Addrerss for T1G_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;T1G_INT = Vector #33
    MOVWF TBLPTRU, ACCESS ;4008h + [(33d) 21h * 2] = 404A
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x4A
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link T1G_INT ISR To Vector Address *** ---
    MOVLW 0x18 ;T1GISR = 0x3060 >> 2 = 0C18h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Create Interrupt Vector Addrerss for U2RX_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;U2RX_INT = Vector #50
    MOVWF TBLPTRU, ACCESS ;4008h + [(50d) 32h * 2] = 406C
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x6C
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link U2RX_INT ISR To Vector Address *** ---
    MOVLW 0x20 ;U2ISR = 0x3080 >> 2 = 0C20h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Create Interrupt Vector Addrerss for T4_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;T4_INT = Vector #56
    MOVWF TBLPTRU, ACCESS ;4008h + [(56d) 38h * 2] = 4078
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x78
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link T4_INT ISR To Vector Address *** ---
    MOVLW 0x38 ;T4ISR = 0x30E0 >> 2 = 0C38h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2
    CLRWDT
    RETURN 1
    ; --- *** Interrupt Service Routines Start Here !!! *** ------------------------------------------------------
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** DMA1 Interrupt Service Routine *** ---
    ; --- *** For U2TX *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    ORG 0x3000
    DmaISR:
    BANKSEL PIR2 ;
    BCF PIR2, 0, 1 ;Clear DMA1SCNTIF
    BCF PIE2, 0, 1 ;Disable DMA1SCNTIE
    ; BSF PIE6, 2, 1 ;Enable U2RXIE
    ; BANKSEL Work
    ; BSF Work, 6, 1 ;pPac = 1
    BANKSEL DMA1CON0
    BCF DMA1CON0, 7, 1 ;Clear DMA1EN
    RETFIE FAST
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** UART1 Interrupt Service Routine *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    ORG 0x3020
    U1ISR: ;ISR code at 0x102A in PFM
    BANKSEL U1ERRIR ;Bank 61
    BTFSC U1ERRIR, 1, 1 ;R1FOIF, Check for overflow error
    BCF U1ERRIR, 1, 1 ;R1FOIF Clear overflow error flag
    BTFSC U1ERRIR, 3, 1 ;R1FERIF, Check for overflow error
    BCF U1ERRIR, 3, 1 ;R1FERIF Clear overflow error flag
    BANKSEL Mail
    BTFSS Mail, 3 ;hInBit
    GOTO U1ISR2
    BSF Mail, 3, 1 ;hInBit = 1
    MOVFF U1RXB, Hin0h ;Move Byt0 from Receive Register to Hin0h
    BANKSEL PIR3 ;Bank 57
    BCF PIR3, 3, 1 ;Clear U1RXIF
    GOTO U1ISR3 ;Go Back Home
    U1ISR2:
    MOVFF U1RXB, Hin1h ;Move Byt1 from Receive Register to Hin1h
    BANKSEL PIR3 ;Bank 57
    BCF PIR3, 3, 1 ;Clear U1RXIF
    BANKSEL Mail ;Bank 0?
    BCF Mail, 3, 1 ;hInBit = 0
    BSF Mail, 2, 1 ;Dat = 1
    U1ISR3:
    RETFIE FAST

    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Timer 1 Interrupt Service Routine *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    ORG 0x3060
    T1GISR:
    MOVFF TMR1L, TachL
    MOVFF TMR1H, TachH
    BANKSEL PIR4 ;Bank 57
    BCF PIR4, 1, 1 ;T1GIF
    BANKSEL Work ;Bank 0?
    BSF Work, 1, 1 ;CPS = 1
    RETFIE FAST
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= *** ---
    ; --- *** Nextion UART2 Interrupt Service Routine *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    ORG 0x3080
    U2ISR:
    ; -=- Start by Clearing Error Flags, If Any -=-
    BANKSEL U2ERRIR ;Bank 61
    BTFSC U2ERRIR, 1, 1 ;R2FOIF, Check for overflow error
    BCF U2ERRIR, 1, 1 ;R2FOIF Clear overflow error flag
    BTFSC U2ERRIR, 3, 1 ;R2FERIF, Check for overflow error
    BCF U2ERRIR, 3, 1 ;R2FERIF Clear overflow error flag
    BANKSEL Mail
    BTFSS Mail, 5 ;nInBit
    GOTO U2ISR2
    MOVFFL U2RXB, Hin0n ;Move U2RXB to Hin0n
    BANKSEL PIR6 ;Bank 57
    BCF PIR6, 2, 1 ;Clear U2RXIF
    BSF Mail, 5, 1 ;nInBit = 1
    GOTO U2ISR3 ;Go Back Home
    U2ISR2:
    MOVFF U2RXB, Hin1n ;Move Byt1 from Receive Register to Hin1n
    BANKSEL PIR6 ;Bank 57
    BCF PIR6, 2, 1 ;Clear U2RXIF
    BANKSEL Mail ;Bank 0?
    BCF Mail, 5, 1 ;nInBit = 0
    BSF Mail, 4, 1 ;NexFlag = 1
    U2ISR3:
    RETFIE FAST ;RETURN
    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Seconds Counter Timer 4 Interrupt Service Routine *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^  *** ---
    ORG 0x30E0
    T4ISR:
    BANKSEL PIR7 ;Bank 57
    BCF PIR7, 0, 1 ;Clear TMR4IF
    ;BANKSEL LATA
    ;BSF LATA, 1, 1 ;Debug Pin 2
    BANKSEL Secs ;Bank 0?
    DECF Secs, F ;Secs -= 1
    RETFIE FAST


    I don't need the world to know my name, but I want to live a life so all my great-grandchildren proudly remember me.
    #5
    1and0
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/19 14:33:20 (permalink)
    +1 (1)
    mpgmike
    Here is a working example for a K42:

    ; --- *** -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- *** ---
    ; --- *** Create Interrupt Vector Addrerss for DMA1SCNT_INT *** ---
    ; --- *** ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ *** ---
    MOVLW 0x00 ;DMA1SCNT_INT = Vector #16
    MOVWF TBLPTRU, ACCESS ;4008h + [(16d) 10h * 2] = 4028
    MOVLW 0x40
    MOVWF TBLPTRH, ACCESS
    MOVLW 0x28
    MOVWF TBLPTRL, ACCESS
    ; --- *** Link DMA1DCNT_INT ISR To Vector Address *** ---
    MOVLW 0x00 ;DMA1DCNTISR = 0x3000 >> 2 = 0C00h
    MOVWF TABLAT, ACCESS
    TBLWT*+
    MOVLW 0x0C
    MOVWF TABLAT, ACCESS
    TBLWT*+
    ; --- *** Write To Non-Volatile Memory *** ---
    BANKSEL NVMCON1
    MOVLW 0x84 ;Setting to write to PFM
    MOVWF NVMCON1
    MOVLW 0x55 ;Required unlock sequence
    MOVWF NVMCON2
    MOVLW 0xAA
    MOVWF NVMCON2
    BSF NVMCON1, WR ;Start writing to PFM
    BTFSC NVMCON1, WR ;Wait for write to complete
    GOTO $-2


    Why are you wasting resources to generate the vector addresses at runtime?  For example, instead of the above, why not do this instead

            org    0x04028
            dw     0x3000 >> 2

    etc.  Better yet, use labels instead of hardcoded addresses.
    #6
    Jerry Messina
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/20 03:45:32 (permalink)
    0
    Why are you wasting resources to generate the vector addresses at runtime?

    The original versions of the datasheet for the K42 (rev A and B) show that horrible method for setting up the vector table in asm. The C examples never did, and it was removed from later datasheets.
     
    #7
    1and0
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/20 06:33:22 (permalink)
    +2 (2)
    Jerry Messina
    The original versions of the datasheet for the K42 (rev A and B) show that horrible method for setting up the vector table in asm. The C examples never did, and it was removed from later datasheets.

    So he was led by the blind. ;)  Another good reason to understand the code instead of blindly copy and use other's code, even if it's from Microchip.
     
    #8
    mpgmike
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    Re: PIC18F46K42 ASSEMBLER INTERRUPTS ARRANGEMENT 2019/07/20 07:51:30 (permalink)
    +1 (1)
    Actually, the posted snippet was an Assembly addition to a PBP BASIC program, and was written right after the K42 release.  I do appreciate the suggestions, I'm taking notes, and plan on revisiting this project in the near future.  I might just play with it a bit, trying what I'm learning.

    I don't need the world to know my name, but I want to live a life so all my great-grandchildren proudly remember me.
    #9
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