Re: 24F08KL302 LPRC running at MUCH lower freq than nominal 31kHz
2019/07/04 20:04:11
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BlindedByDaLight
Is my math wrong?
Nothing wrong with your math. I dug up a PIC24F16KL402 (that I had evaluated some time ago but never used in a project) and plugged it into my breadboard. With your WDT settings I got a timeout of 1.92 seconds, which is about 91% of the nominal 2.11 seconds predicted by your math and WDT settings.
A couple of comments:
- I have never used a WDT as a "precise" timer. I have used a WDT to try to recover after some "glitch" (peripheral hardware failure; transient electrical problem; cosmic ray; etc.) Exact timing was not an issue.
- For test purposes I can't think of a single reason to run a 16-bit PIC with a master clock of 31 kHz. I usually run at full speed (32 MHz for this chip), but for testing and evaluation I sometimes use the fastest speed that I can get from configuration pragmas without having to write to registers. (But see Footnote.)
Anyhow...
Here's my test program. Note that I put what I think is pretty much an absolute minimum amount of code so that the timing measurement wouldn't be confused by user initialization code or other user code.
// PIC24F16LK402 WDT timing test program
// Clock 16 MHz:
// FRC (with default RCDIV) + PLL
// Connections
// PIC24F16KL402 28-pin DIP
// LED2 is RB1 (Pin 5 of the DIP28)
// PIC24F16KL402 Configuration Bit Settings
// FBS
#pragma config BWRP = OFF // Boot Segment Write Protect (Disabled)
#pragma config BSS = OFF // Boot segment Protect (No boot flash segment)
// FGS
#pragma config GWRP = OFF // General Segment Flash Write Protect (General segment may be written)
#pragma config GSS0 = OFF // General Segment Code Protect (No Protection)
// FOSCSEL
#pragma config FNOSC = FRCPLL // Oscillator Select (Fast RC Oscillator with Postscaler and PLL (FRCDIV+PLL))
#pragma config SOSCSRC = ANA // SOSC Source Type (Analog Mode for use with crystal)
#pragma config LPRCSEL = HP // LPRC Power and Accuracy (High Power/High Accuracy)
#pragma config IESO = ON // Internal External Switch Over bit (Internal External Switchover mode enabled (Two-speed Start-up enabled))
// FOSC
#pragma config POSCMD = NONE // Primary Oscillator Mode (Primary oscillator disabled)
#pragma config OSCIOFNC = ON // CLKO Pin I/O Function (Port I/O enabled (CLKO disabled))
#pragma config POSCFREQ = HS // Primary Oscillator Frequency Range (Primary Oscillator/External Clock frequency >8MHz)
#pragma config SOSCSEL = SOSCHP // SOSC Power Selection Configuration bits (Secondary Oscillator configured for high-power operation)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switching and Fail-safe Clock Monitor Enabled)
// FWDT
#pragma config WDTPS = PS512 // Watchdog Timer Postscale Select bits (1:512)
#pragma config FWPSA = PR128 // WDT Prescaler bit (WDT prescaler ratio of 1:128)
#pragma config FWDTEN = ON // Watchdog Timer Enable bits (WDT enabled in hardware)
#pragma config WINDIS = OFF // Windowed Watchdog Timer Disable bit (Standard WDT selected (windowed WDT disabled))
// FPOR
#pragma config BOREN = BOR3 // Brown-out Reset Enable bits (Enabled in hardware; SBOREN bit disabled)
#pragma config PWRTEN = ON // Power-up Timer Enable (PWRT enabled)
#pragma config I2C1SEL = PRI // Alternate I2C1 Pin Mapping bit (Default SCL1/SDA1 Pins for I2C1)
#pragma config BORV = V18 // Brown-out Reset Voltage bits (Brown-out Reset at 1.8V)
#pragma config MCLRE = ON // MCLR Pin Enable bit (RA5 input disabled; MCLR enabled)
// FICD
#pragma config ICS = PGx1 // ICD Pin Placement Select (EMUC/EMUD share PGC1/PGD1)
#include <xc.h>
// LEDS: LED1 is RB1 (Pin 5 of the DIP28)
#define LED1_TRIS TRISBbits.TRISB1
#define LED1 LATBbits.LATB1
// FRCPLL with default RCDIV of 1:2 gives system clock = 16 MHz
#define FCY 8000000UL
#include <libpic30.h>
int main()
{
LED1 = 0;
LED1_TRIS = 0;
__delay_ms(100);
ClrWdt();
LED1 = 1;
Sleep();
// XC16 generates return to a break;reset sequence
// or you could have the following
//asm(" reset");
return -1;
} // End of main()
Result: LED periodic output was On for 1.92 seconds and Off for 100 milliseconds.
Regards,
Dave
Footnote:
I changed the system clock to be LPRC as you had it. Results were about the same: Still got 1.92 second WDT timeout.
post edited by davekw7x - 2019/07/04 20:09:24
Sometimes I just can't help myself...