[PIC18F K42] "Slow" PWM - [ANSWERED]
- I'm using SMT1 clocked at Fosc/4 in Timer Mode with a period of (508 * 525) - 1
- SMT1_out is fed into CLC1 (just Gate #0, the other Gates are unused, 4-way AND)
- CLC1_out is used to trigger TMR4 in Monostable Mode (rising edge of CLC1_out)
- PWM7 uses TMR4 to produce the desired LOW-pulse
Thanks again to mbrowning and NorthGuy! :-)[EDIT END]
After a loooooong abstinence from the 8-bit PIC world, I've decided to give it another try.
I'm using the PIC18F47K42
running @ 16MHz to generate a VGA signal.
- SPI + DMA output the pixel data
- TMR2 and PWM5 are generating the horizontal sync signal
- TMR4 and PWM7 are generating the vertical sync signal
TMR2 is being clocked by Fosc/4 with a prescaler of 4, PR2 is set to 126, so the period is (4 * 127) = 508 instructions cycles.
After each period an interrupt is fired. As part of the interrupt service routine either the DMA is triggered (visible part of the frame) or TMR4 + PWM7 are started (one shot, during the invisible part of the frame).
Everything is working fine, but having to deal with TMR4/PWM7 in the interrupt service routine is unnecessary overhead.
It should be possible to have a rather "slow" PWM that is set up once at start-up and running "purely in hardware" after that.
One period of this PWM would be (525 * 508) = 266,700 cycles long.
The PWM's HIGH time needs to be (523 * 508) = 265,684 cycles, the LOW time (2 * 508) = 1016 cycles.
When I say "cycles", I'm referring to instruction clock cycles i.e. Fosc/4
With a prescaler of 4, these numbers can be reduced a bit, i.e. (525 * 127) = 66,675 (Fosc/16) cycles for the period,
66,421 cycles for the PWM HIGH time, and 254 cycles for the LOW time.
I have thought of concatenating two timers, where one timer's overflow output serves as clock input to the second timer.
But this second timer needs to be a 16-bit timer (1 period = 525 clocks), have a settable period, and be PWM-capable.
As far as I know, the 16-bit timers TMR1/3/5 are neither PWM-capable nor do they have a period register.
I suppose "crazy" constructions such as using TMR1 together with CCP1 (toggle output) and CCP2 (toggle output and reset TMR1) and fusing the CCPx outputs via CLC to produce a PWM are possible, but this seems quite cockamamie.
Is there a simple, elegant solution which I have missed?
post edited by peter.einramhof - 2019/06/28 16:20:26