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High Resolution PWM with Auxiliary Clock APLL not working

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phill_
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2019/06/25 00:39:39 (permalink)
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High Resolution PWM with Auxiliary Clock APLL not working

Hello,
 
im currently trying to use my PWM generators with High Resolution Mode (HREN).
In order to fuction correctly the need a clock signal with a frequency of 500Mhz, therefor I was trying to use the Auxiliary Clock Module with the FRC as a clock source.
After two days it still does not want to work as i wanted.
 
Im working on a dsPIC33CK256MP205
Im always getting a: "Generic Soft Trap Vector" which has been activated by:
INTCON3>bit0(Auxiliary PLL Loss of Lock Soft Trap Status bit()
 
But my Auxiliary Clock register ACLKCON1 tells me that
APLLEN = 1;
APLLCK = 1;
ASRCSEL = 0;
FRCSEL = 1;
APLLPRE = 000001;
So it should work i gues..
 
Hopefully someone is able to tell me what iam doing wrong.
 
CODE:
CLKDIV = 0x3001;
PLLFBD = 0x7D;
OSCTUN = 0x00;
PLLDIV = 0x21;
ACLKCON1 = 0x8101;
APLLFBD1 = 0x7D;
APLLDIV1 = 0x121;
REFOCONL = 0x00;
REFOCONH = 0x00;
RPCON = 0x00;
PMDCON = 0x00;
PMD1 = 0x00;
PMD2 = 0x00;
PMD3 = 0x00;
PMD4 = 0x00;
PMD6 = 0x00;
PMD7 = 0x00;
// DMTMD enabled; CLC3MD enabled; OPAMPMD enabled; BIASMD enabled; CLC4MD enabled; SENT2MD enabled; SENT1MD enabled; CLC1MD enabled; CLC2MD enabled;
PMD8 = 0x00;
// CF no clock failure; NOSC FRC; CLKLOCK locked; OSWEN Switch is Complete;
__builtin_write_OSCCONH((uint8_t) (0x00));
__builtin_write_OSCCONL((uint8_t) (0x80));
#1

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    JPortici
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    Re: High Resolution PWM with Auxiliary Clock APLL not working 2019/06/25 02:19:17 (permalink)
    4 (2)
    Groan, Translating register values and hex... The bitfield is there to make things more readable for me and for the you of tomorrow (altough some times you NEED to write specific bits together)
     
    Two or three bad things:
    - You are enabling the PLL (APLLEN bit) BEFORE setting the divider and feedback. You should configure the PLL before enabling it, the current configuration may not be a working one.
    - i'm not sure is if you're feeding FRC or FRCDIV, Because FRCDIV (4MHz) is outside the required frequency range (8-64 MHz)
    - The PLL won't start until a peripheral requires it so you need to set the PWM clock prior to enabling APLL. This shouldn't cause a trap though, this should just make you wait for eternity for the LOCK bit to be set
    #2
    phill_
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    Re: High Resolution PWM with Auxiliary Clock APLL not working 2019/06/25 06:51:34 (permalink)
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    Hello JPortici,
     
    first thank you for your fast answer.
    I changed the order of configuration and APLLEN Bit.
     
    Im not sure but testwise i changend OSC2 to clock out pin and when I use my Oscilloscope and measure the frequency I get 4MHz instead of 8. Im not sure if the Freqeuency on this pin ist the same as the internal but if so
    that would be my problem.
     
    Im not sure what you mean with the PWM prior enablig APLL, do you just mean setting that bit to 1?
     
     
    #3
    JPortici
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    Re: High Resolution PWM with Auxiliary Clock APLL not working 2019/06/25 08:43:14 (permalink)
    5 (1)
    I suggest you read the Oscillator reference manual chapter first. The current version which you will find in the pic product page, documents section is DS70005255B
     
    to sum it up
    - If the OSCO pin is used to output a frequency in FRC or EC mode, it will actually output Fp, so it's correct that you see 4 MHz on OSCO
    - You can enable the PLL, but it won't start until a peripheral requests its clock from the PLL. So, in your case, the lock bit won't be set until you also configure the HSPWM to be clocked from APLL by writing the appropriate value to the PCLKCON register.. HOWEVER this shouldn't cause the issue you're having. I still think that there is a problem in your Clock+PLL configuration
     
    This is working code from a sample program i wrote to test the HSPWM in the dsPIC33CH128MP508. The (master) core, the oscillator and the HSPWM are 100% the same between the pic i used and your pic.
    The only difference is that i have used an external clock source instead of FRC, but the EC was also 8MHz
    //Oscillator Configuration: EC+PLL, 100MHz
      CLKDIVbits.PLLPRE = 1;      //N1 = 1   -> FPFD = 8 MHz
      PLLFBDbits.PLLFBDIV = 125;  //M  = 125 -> FVCO = 1GHz
      PLLDIVbits.POST1DIV = 5;    //N2 = 5
      PLLDIVbits.POST2DIV = 1;    //N3 = 1   -> FPLLO = 200MHz -> FPLLO/2 = 100MHz
      // Initiate Clock Switch to EC+PLL (NOSC=0b011)
      __builtin_write_OSCCONH(0x03);
      __builtin_write_OSCCONL(OSCCON | 0x01);
      // Wait for Clock switch to occur
      while (OSCCONbits.OSWEN!= 0);
     
      //AFVCO = 1.6 GHz and AFPLLO = 100 MHz using 8 MHz EC
      // Configure the source clock for the APLL
      ACLKCON1bits.FRCSEL = 0;        //Clock is POSC
      // Configure the APLL prescaler, APLL feedback divider, and both APLL postscalers.
      ACLKCON1bits.APLLPRE = 1;       //N1 = 1
      APLLFBD1bits.APLLFBDIV = 200;   //M = 200
      APLLDIV1bits.APOST1DIV = 5;     //N2 = 5
      APLLDIV1bits.APOST2DIV = 4;     //N3 = 4
      // Enable APLL
      ACLKCON1bits.APLLEN = 1;
     

      //Set Up Clock
      PCLKCON = 0;
      PCLKCONbits.MCLKSEL = 1;      //AFVCO/2 - 500 MHz
     
    //  while(!PCLKCONbits.HRRDY);
     
      PG1CONL = 0;
      PG1CONLbits.CLKSEL = 1;
      PG1CONLbits.HREN = 0;
      PG1CONH = 0;
      PG1IOCONHbits.PENL = 1;
     
      PG4CONL = 0;
      PG4CONLbits.CLKSEL = 1;
      PG4CONLbits.HREN = 1;
      PG4CONH = 0;
      PG4IOCONHbits.PENL = 1;
     
      PG1PER = 1000 - 1;
      PG1DC = 500;
     
      PG4PER = 1000 - 1;
      PG4DC = 500;
     
      PG1CONLbits.ON = 1;
      PG4CONLbits.ON = 1;
     

    #4
    phill_
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    Re: High Resolution PWM with Auxiliary Clock APLL not working 2019/06/26 05:04:09 (permalink)
    0
    Solved it.
     
    I changed the clocksource to an external 12MHz quarz crystal and the auxiliary clock and the hspwm worked right away. You were right with your idea that the internal FRC oscillator might not work.
    I also implemented your code and it also worked like a charm.
     
    Thank you :)
    #5
    JPortici
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    Re: High Resolution PWM with Auxiliary Clock APLL not working 2019/06/26 06:00:17 (permalink)
    0
    I don't remember if i have tried the APLL with FRC. FRC with the main PLL does work.
     
    Have you tried with FRCDIV bits = 0 so FRCDIV frequency is 8MHz?
     
    Because, according to errata #5
    5. Module: Oscillator
    When using the 8 MHz internal FRC Oscillator with Primary PLL as either a system clock or
    a peripheral source, FRCDIVN drives the PLL instead of the FRC.
    This means that the PLL FRC input selection issubject to the FRCDIV<2:0> bits and could lead
    to a condition where the minimum PLL inputrequirement of 8 MHz is not maintained.
     
    Workaround
    Ensure FRCDIV<2:0> bits are maintained aszero when using FRCPLL as either a system
    clock or a peripheral source.

     
    This affects the main PLL but i wouldn't be surprised if it affected the Aux PLL too.
    post edited by JPortici - 2019/06/26 06:04:04
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