PIC16F19197 (95/96/97) SMT Counter Mode operation
The SMT (Signal Measurement Timer) is a wonder peripheral with capabilities that are not only convenient, but that increase data capture accuracy as well. It has many different "modes" of operation.
In Counter Modes, the SMT1 module uses the SMT1SIG (Signal) input as the timer clock and the SMT1WIN input as the capture interval signal. For the simplest of these, "Counter Mode" (neither Gated nor Windowed), documentation in the PIC16(L)F19195/6/7 data sheet (section 28.7.9 COUNTER MODE) says:
"... SMTxCPW register will be updated with the current SMTxTMR value on the rising edge of the SMTxWIN input. See Figure 28-18."
That figure shows the CPW register updating on the falling edge
of SMTxWIN. So, some questions:
- Which is correct, rising edge or falling edge? Is this not, in fact, affected/determined by SMT1CON0.WPOL?
- Does this behavior (corrected) apply to ALL Counter modes of this module (all modes where the SMT1SIG input is acting as the timer clock and SMT1WIN is the capture interval trigger)?
- Documentation (including wave form diagrams) show that "non-Counter" modes add a synchronization delay to the SMT1WIN and SMT1SIG signals. Conversely, does this mean there is NO rise/fall detection delay in the Counter modes? In other words, can the SMT perform true asynchronous captures (SMT1SIG as the clock and SMT1WIN as the capture trigger) when used in a Counter mode?