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Hot!Operation of PIC ADCs with Vref+ less than 1.8V???

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Oooh_nice_shed
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2019/06/12 06:26:26 (permalink)
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Operation of PIC ADCs with Vref+ less than 1.8V???

Hi All,
 
Does anybody know of the implications of operating the ADC with a positive reference voltage  of less than 1.8V?
 
The specific devices of interest to me are PIC16LF18323/18324/18325/18326. The datasheet for all of these devices states that the positive ADC reference voltage ADREF+ must lie in the range of 1.8V to VDD. I suspect that this is also the case for many more PIC devices. Ideally I would like to use a +ve reference generated by the FVR, but VDD is only 2.0V and so the only permissible FVR voltage is 1.024V - clearly well below the 1.8V datasheet limit.
 
Initial tests (with ADREF+ = 1.024V) indicate that in some cases I can achieve the sort of measurement accuracy that one could expect from a 10-bit ADC, but in others cases I do indeed get a large measurement error (perhaps 10%). So far I haven't been able to discover what influences this error.
 
Can anybody tell me:
 
1.    What is it about the ADC which dictates the 1.8V lower limit for ADREF+?
2.    What are the implications of using ADREF+ of less than 1.8V?
 
Thanks in advance.
 
#1

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    btbass
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 07:27:26 (permalink)
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    With a resolution of 1mV, could it just be noise on the input signal that is the problem?
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    Oooh_nice_shed
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 07:35:47 (permalink)
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    The measurement error I'm seeing is of the order of up to about 10% of ADC full scale. This equates to a maximum error count of about 102 out of the total 1024 (10-bit) ADC count. When I see the error, it is repeatable and I'm as confident as I can be that it isn't noise related.
     
    My real issue here is trying to understand the mechanism behind the 1.8V lower limit on the +ve threshold voltage and the implications of using a lower voltage. My suspicion is that it is related to the minimum enhancement voltage required by FETs inside the device which connect the FVR to the various internal peripherals, but this is conjecture on my part.
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    JPortici
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 07:36:27 (permalink)
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    i wonder if the input range of the VREF buffer is the limiting factor?
    post edited by JPortici - 2019/06/12 07:37:38
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    Chris A
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 07:49:26 (permalink)
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    Option to use VDD as +ref and calibrate VDD by reading FVR as input?
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    Oooh_nice_shed
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 08:46:55 (permalink)
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    Thanks. I'd already homed in on the use of VDD as +ve reference and this is probably what I'll end up doing.
     
    I'm still seeking knowledge however. Although I can put workarounds in place (some not ideal in this particular application),. I'd really like to understand the finer points of the 1.8V limit for future reference
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    davea
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 17:59:59 (permalink)
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    *****
    post edited by davea - 2019/06/12 18:02:47
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    dan1138
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/12 19:29:57 (permalink)
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    Oooh_nice_shed
    Thanks. I'd already homed in on the use of VDD as +ve reference and this is probably what I'll end up doing.
     
    I'm still seeking knowledge however. Although I can put workarounds in place (some not ideal in this particular application),. I'd really like to understand the finer points of the 1.8V limit for future reference



    Most of Microchips ADC implementations are of a ratio-metric kind. This loosely means that digital value represents the ratio between the input voltage and the reference voltage. This kind of ADC places a limit on the minimum voltage difference between VREF+ and VREF-. For Microchip this is specified as 1.8 volts for the device you are using.
     
    Why this limit is 1.8 volts I do not know for certain. At a guess there may be an issue when the digital conversion steps are less than 1.8/1024 volts the digital output code may become undecidable. Something like this may result in a massive conversion error. Like I said this is a guess, I have no facts to back this up. This may be related to the minimum voltage that the analog circuitry of the ADC can operate at and hold the accuracy and noise specifications.
    post edited by dan1138 - 2019/06/12 19:31:47
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    Oooh_nice_shed
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/13 00:59:17 (permalink)
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    Thanks dan1138 for your input.
     
    Part of my concern here and my desire for a better understanding of the underlying mechanics is that I'd like to be able to assess the implications for other analogue peripherals in the device.
     
    For example, the DAC may also use the FVR at 1.024V for its upper reference voltage and once again the FVR voltage is connected by way of a MUX presumably in a similar manner to that used for the ADC. If the mux switching is achieved by FETs which are perhaps not fully enhanced when the incoming voltage is less than 1.8V (which might explain the datasheet limitation), then perhaps the same 1.8V limitation applies to the DAC +ve reference. Although there is no such limitation specified for the DAC in the datasheet, perhaps the datasheet is incomplete in this respect. I stress that the statement about FETs not being fully enhanced is conjecture on my part.
     
    Given that I'd ideally like to use the the DAC with VDD=2V and Vref+ = 1.024V from the FVR, my quest for deeper understanding continues.
     
    Interestingly, the datasheet values for total ladder resistance for the DAC and ADC are:
     
    DAC:    6k ("Unit resistor value") x 32 = 192k
    ADC:    50k ("Voltage reference ladder impedance")
     
    So, it might be reasonable to guess that the unwanted voltage drop across a partly-enhanced MUX FET would be greater when using the ADC (due to higher ladder current) than when using the DAC. This might in turn cause a greater error when using the ADC than when using the DAC. And, just maybe, this could be why the 1.8V Vref+ limitation isn't stated for the DAC (although is this is the case then surely we would be in a grey area of FET tempco if we are indeed in a partial enhancement region - another possible pitfall).
     
    Still searching for wisdom....... Any Microchip PIC chip designers out there?
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    Chris A
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/13 04:26:54 (permalink)
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    The stability/accuracy of the FVR also needs to be assessed.  Probably not the same devices but I have noticed various threads in the past where people have had issues using it.  One thread had a lot of testing shown. 
     
    In my low volume world that has indicated to me - don't try to use it!
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    Oooh_nice_shed
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    Re: Operation of PIC ADCs with Vref+ less than 1.8V??? 2019/06/13 05:15:37 (permalink)
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    Thanks Chris A.
     
    I too know of the of issues with the FVR and the VDD/FVR level tradeoffs. I believe that in some cases PIC datasheets have become updated with additional data regarding this sort of thing as issues have become apparent whilst devices are in the public domain.
     
    I tend to develop PIC-based applications which are often fairly demanding of the analogue peripherals and which may use them in unconventional ways. Hence I am always looking to gain a level of understanding beyond the datasheet info.
    #11
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