Re: Operation of PIC ADCs with Vref+ less than 1.8V???
Thanks dan1138 for your input.
Part of my concern here and my desire for a better understanding of the underlying mechanics is that I'd like to be able to assess the implications for other analogue peripherals in the device.
For example, the DAC may also use the FVR at 1.024V for its upper reference voltage and once again the FVR voltage is connected by way of a MUX presumably in a similar manner to that used for the ADC. If the mux switching is achieved by FETs which are perhaps not fully enhanced when the incoming voltage is less than 1.8V (which might explain the datasheet limitation), then perhaps the same 1.8V limitation applies to the DAC +ve reference. Although there is no such limitation specified for the DAC in the datasheet, perhaps the datasheet is incomplete in this respect. I stress that the statement about FETs not being fully enhanced is conjecture on my part.
Given that I'd ideally like to use the the DAC with VDD=2V and Vref+ = 1.024V from the FVR, my quest for deeper understanding continues.
Interestingly, the datasheet values for total ladder resistance for the DAC and ADC are:
DAC: 6k ("Unit resistor value") x 32 = 192k
ADC: 50k ("Voltage reference ladder impedance")
So, it might be reasonable to guess that the unwanted voltage drop across a partly-enhanced MUX FET would be greater when using the ADC (due to higher ladder current) than when using the DAC. This might in turn cause a greater error when using the ADC than when using the DAC. And, just maybe, this could be why the 1.8V Vref+ limitation isn't stated for the DAC (although is this is the case then surely we would be in a grey area of FET tempco if we are indeed in a partial enhancement region - another possible pitfall).
Still searching for wisdom....... Any Microchip PIC chip designers out there?