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Hot!I cannot initialise ADC Core 0 and Core 1 and make them both work

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JRtoujours
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2019/05/22 23:55:17 (permalink)
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I cannot initialise ADC Core 0 and Core 1 and make them both work

Hello, I am newby at microcontroller. I have a question: 
I am trying to initialise core 0 and core 1 of the ADC module, each with its Interrupt routine.
the problem is that the core 0 work well but the core 1 not. the core 1 only works when I remove the core 0 initialisation. I think they might be a bit register I am missing to set but I have no idea what it might be. I will appreciate any inside from you guys. Thank you.
// <editor-fold defaultstate="collapsed" desc="Start">
//#include "PFC_ViennaBridge.h"
#include "p33EP64GS504.h"
#include "xc.h"
#include "math.h"
#include "dsp.h" // Database-Supported Haskell
#include "stdio.h" // For Syntax like printf, scanf usw
#include "stdlib.h"
#include "PFC_ViennaBridge.h"
#include<libpic30.h>
#include "COM_0_07.h" //for flash erase/write

///**************************************************************************************************/
///* Configuration Bits */
///**************************************************************************************************/
// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)

// FBSLIM
// BSLIM = No Setting

// FOSCSEL
#pragma config FNOSC = PRIPLL // Oscillator Source Selection (Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL))
#pragma config IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FOSC
#pragma config POSCMD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config IOL1WAY = ON // Peripheral pin select configuration bit (Allow only one reconfiguration)
#pragma config FCKSM = CSDCMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)
#pragma config PLLKEN = ON // PLL Lock Enable Bit (Clock switch to PLL source will wait until the PLL lock signal is valid)

// FWDT
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
#pragma config WDTEN = OFF // Watchdog Timer Enable bits (WDT and SWDTEN disabled)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)

// FICD
#pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
#pragma config BTSWP = ON // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is enabled)

// FDEVOPT
#pragma config PWMLOCK = OFF // PWMx Lock Enable bit (PWM registers may be written without key sequence)
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config DBCC = OFF // DACx Output Cross Connection bit (No Cross Connection between DAC outputs)

// FALTREG
#pragma config CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)

// FBTSEQ
#pragma config BSEQ = 0x005 // Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active
#pragma config IBSEQ = 0xFFA // The one's complement of BSEQ; must be calculated by the user and written during device programming.

// FBOOT
#pragma config BTMODE = DUAL // (Device is in dual partition mode)
// </editor-fold>

void init_OSC(void) //Fosc=Fin*(M/(N1*N2))=8MHz*(40/(2*2))=80MHz --> Fcy=40MHz
{
    CLKDIVbits.PLLPRE = 0; //N1 = PLLPRE + 2
    PLLFBD = 38; //M = PLLFBD + 2
    CLKDIVbits.PLLPOST = 0; //N2 = PLLPOST + 2
    while(OSCCONbits.LOCK!=1){}; //wait for PLL to lock
    ACLKCONbits.ASRCSEL = 1; //Primary Oscillator as clock source FRC
    ACLKCONbits.FRCSEL = 0; //Input clock determined by ASRCSEL
    ACLKCONbits.SELACLK = 1; //select auxiliary PLL or osc to provide the source clock for Aux clock divider
    ACLKCONbits.APSTSCLR = 0b111; //Postscaler 1
    ACLKCONbits.ENAPLL = 1; //Enable APLL --> 128MHz
    while(ACLKCONbits.APLLCK != 1){}; //wait until APLL is locked
}
void init_TR1(void)
{
// T1CONbits.TON = 0; //Timer 1 disabled
    T1CONbits.TCS = 0; //Internal clock
    T1CONbits.TCKPS = 0; //Prescaler 1/8
// T1CONbits.TGATE = 0; // Disable Gated Timer mode
     TMR1 = 0; //reset timer counter
     PR1 = 100E-6 * FCY; //Load period value: PeroidTime*FCY = PR1 = 100µs*40MHz until Timer1 overflow.100E-6 *
 
     IPC0bits.T1IP = 5; //Timer 1 Interrupt priority 5
     IFS0bits.T1IF = 0; //Clear Timer 1 Interrupt flag
     IEC0bits.T1IE = 1; // Enable Timer1 interrupt fire interrupts overflow when from 2E16 to 0
     T1CONbits.TON = 1; //Timer 1 enabled
     
    INTCON2bits.GIE = 1; // Global Interrupt Enable
}
void init_IOs(void)
{
    PORTA = 0; // All pins are set low
    ANSELA = 0b0000000000000111; //Register are digital but 0, 1, 2
    TRISA = 0b0000000000000111; // Register are outpout but 0, 1, 2
    
    PORTB = 0; // All pins are set low
    ANSELB = 0b0000011000010001; // Register are digital but 0, 4, 9, 10
    TRISB = 0b0000011000010001; // Register are output but 0, 4, 9, 10
    LATB = 0b0000000000000000; // Controls the output level of the port
    
    PORTC = 0; // All pins are set low
    TRISC = 0b0000111000000010; // Register are digital but 1, 9, 10, 11
    ANSELC = 0b0000111000000010; // Register are output but 1, 9, 10, 11
    LATC = 0b0000000000000000; // Controls the output level of the port
    
    RPOR9bits.RP51R = 0b110011; // assigned PWM4H to RP51, pin 5
}
void init_ADC(void) //Comments to save flash memory (settings are the same as startup values)
{
   

    ADCON1Lbits.ADON = 1; //ADC module enabled
    ADCON5Hbits.WARMTIME = 0b1111; //Set longest power-up time
    
    ADCON5Lbits.C0PWR = 1; //Core 0 powered
    while(ADCON5Lbits.C0RDY==0); //wait until core 0 is ready
    ADCON3Hbits.C0EN = 1; //Core 0 enabled
    
    ADCON5Lbits.C1PWR = 1; //Core 1 powered
    while(ADCON5Lbits.C1RDY==0); //wait until core 1 is ready
    ADCON3Hbits.C1EN = 1; //Core 1 enabled
ADCAL0Lbits.CAL1EN = 1; //Enable calibration for the dedicated core 1
// ADCAL0Lbits.CAL1DIFF = 0; //Single-ended input calibration
    ADCAL0Lbits.CAL1RUN = 1; //Start calibration
    while(ADCAL0Lbits.CAL1RDY==0); //Poll for the calibration end
    ADCAL0Lbits.CAL1DIFF = 1; //Differential input calibration
    ADCAL0Lbits.CAL1RUN = 1; //Start calibration
    while(ADCAL0Lbits.CAL1RDY==0); //Poll for the calibration end
    ADCAL0Lbits.CAL1EN = 0; //End the core 1 calibration
    
    
    
    ADIELbits.IE0 = 1; //Enable AN0 interrupt (UZK)
    IPC27bits.ADCAN0IP = 6; //AN0 Interrupt Priority 6
    IFS6bits.ADCAN0IF = 0; //Clear AN0 interrupt flag
    IEC6bits.ADCAN0IE = 1; //Enable AN0 interrupt
//
    ADIELbits.IE1 = 1; //Enable AN1 interrupt (UL3)
    _ADCAN1IP = 5; //AN1 Interrupt Priority 5
    _ADCAN1IF = 0; //Clear AN1 interrupt flag
    _ADCAN1IE = 1; //Enable AN1 interrupt
    
    ADTRIG0Lbits.TRGSRC1 = 0b01100; //AN1 trigger source: Common software trigger
    ADTRIG0Lbits.TRGSRC0 = 0b01100; //AN0 trigger source: Timer1 period match
}
void __attribute__((interrupt, no_auto_psv))_ADCAN0Interrupt(void) //every Timer 1 match
{
    LED_YELLOW ^=1;
    _ADCAN0IF = 0; // Clear AN0 interrupt flag
}
void __attribute__((interrupt, no_auto_psv)) _ADCAN1Interrupt(void) //every Timer 1 match
{
    LED_RED ^= 1;
    _ADCAN1IF = 0; // Clear AN1 interrupt flag
}

int main()
{
    init_OSC();
    init_IOs();
    init_TR1();
    init_ADC();
// LED_YELLOW = !LED_YELLOW;
     while(1) { }
 }



#1

2 Replies Related Threads

    MBedder
    Circuit breaker
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    Re: I cannot initialise ADC Core 0 and Core 1 and make them both work 2019/05/23 00:38:11 (permalink)
    0
    DatasheetSet the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when ADON = 1 will result in unpredictable behavior.

    #2
    paulmtcuk
    Junior Member
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    Re: I cannot initialise ADC Core 0 and Core 1 and make them both work 2020/03/24 06:36:16 (permalink)
    0
    bump - since I am suffering a similar issue (albeit simulator related)
     
    seems the example code for ADC (DS70005213F-page 58) is also similar to the above - If you mind asking, how do you know core 1 is not working ? what is it doing differently?
    post edited by paulmtcuk - 2020/03/24 06:44:49
    #3
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